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Participant
Participant
10,659 Views
Registered: ‎08-31-2007

Vivado 2014.3 Simulation Error

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Every time I attempt to launch a simulation in my Vivado 2014.3 Design Edition project, I run into the following error. Same files synthesize just fine and simulate just fine in ISE 14.6.

 

I have rebulit the project multiple times with the same problem. I've even built a simulation only project to no avail. I appreciate any assistance on this issue.

 

launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_message_proc' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
ERROR: [Common 17-161] Invalid option value '' specified for 'object'.

while executing
"get_property "FILE_TYPE" [lindex [get_files -quiet -all $file] 0]"
("foreach" body line 3)
invoked from within
"foreach file $::tclapp::xilinx::xsim::l_compile_order_files {
if { [usf_is_global_include_file $global_files_str $file] } { continue }
..."
(procedure "usf_get_files_for_compilation_behav_sim" line 38)
invoked from within
"usf_get_files_for_compilation_behav_sim $global_files_str"
(procedure "::tclapp::xilinx::xsim::usf_get_files_for_compilation" line 12)
invoked from within
"::tclapp::xilinx::xsim::usf_get_files_for_compilation global_files_str"
(procedure "usf_xsim_setup_simulation" line 35)
invoked from within
"usf_xsim_setup_simulation"
(procedure "tclapp::xilinx::xsim::setup" line 15)
invoked from within
"tclapp::xilinx::xsim::setup { -simset sim_1 -mode behavioral -run_dir C:/<dir info> "

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Xilinx Employee
Xilinx Employee
18,633 Views
Registered: ‎10-24-2013

Hi @skwoods 
This is a known issue in 2014.3

This error occurs on both Windows and Linux systems. This issue is due to:

1) There is a space in the project directory path (e.g. C:\project\project space\project1)

2) There is a simulation source file that contains a space in the file name (e.g. project test tb.vhd)

Correcting the path/filename such that there are no spaces allows the simulation to begin.

This issue will be fixed in 2014.4

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
18,634 Views
Registered: ‎10-24-2013

Hi @skwoods 
This is a known issue in 2014.3

This error occurs on both Windows and Linux systems. This issue is due to:

1) There is a space in the project directory path (e.g. C:\project\project space\project1)

2) There is a simulation source file that contains a space in the file name (e.g. project test tb.vhd)

Correcting the path/filename such that there are no spaces allows the simulation to begin.

This issue will be fixed in 2014.4

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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Participant
Participant
10,630 Views
Registered: ‎08-31-2007
You're correct. I had overlooked one space in a directory name when I went through double checking that. Thanks.
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Observer
Observer
10,482 Views
Registered: ‎01-23-2013
Is there an AR associated with this problem? I'm having the same issue and this is the only mention I've found of it.
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Xilinx Employee
Xilinx Employee
10,473 Views
Registered: ‎10-24-2013

Hi @kpage ,

 

Yes, there is an AR for this and not yet relased for public access. The current status of that AR is "awaiting for release".

Thanks,Vijay
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