11-17-2016 07:52 AM
It appears that the Vivado 2016.3 simulator erroneously uses the VHDL-2008 IEEE library even when the source file type is "regular" VHDL and not VHDL 2008. The synthesizer does not suffer from this problem - it uses the correct IEEE library.
To reproduce: add the content below to a new source file of Type VHDL (NOT VHDL 2008) in a new Vivado 2016.3 RTL project. Run simulation with this entity as the top-level. Simulation is able to compile the file without error, which it should not be able to do since the "and" operator is not defined for the provided argument types in the VHDL-2002 version of ieee.numeric_std (but it is defined for the provided argument types in VHDL-2008 ieee.numeric_std). Then run synthesis. Synthesis stops and reports the following error: [Synth 8-944] 0 definitions of operator "and" match here ["test.vhd":10]. This is the correct and expected behavior.
This appears to be a bug with the Vivado 2016.3 simulator. The Vivado 2016.2 simulator does not suffer from this problem. Can someone from Xilinx please respond? Is there a way I can submit a formal bug report?
Here is the test source file content.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is end entity test; architecture stub of test is begin assert (std_logic'('1') and unsigned'("1")) = unsigned'("1"); end architecture stub;
11-17-2016 10:20 AM
11-17-2016 12:44 PM
Thank you for the response, Balkrishan. Unfortunately, I do not see how that problem is related in any way to this one. The problem I am reporting has nothing to do with defining the type of literals. Rather, the problem is that the Vivado 2016.3 synthesizer is using the VHDL-2008 version instead of the VHDL-2002 version of the IEEE library. I used literals in my example for succinctness, but perhaps a different example will be more clear.
Consider the following.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is end entity test; architecture stub of test is constant sl : std_logic := '1'; constant uns : unsigned := "1"; signal sig : unsigned(0 to 0); begin sig <= ieee.numeric_std."and"(sl, uns); end architecture stub;
The "and" operator does not exist for these argument types in the 2002 version of ieee.numeric_std. Therefore, the Vivado simulator and synthesizer should both object to this usage. As expected, the synthesizer reports this error: "[Synth 8-2778] type error near sl ; expected type unsigned [test.vhd:15]" because it cannot resolve this operator for these types. However, the simulator compiles the file just fine and runs with no complaints. This means that the simulator is able to find this operator defined for these data types in ieee.numeric_std. This is incorrect for 2002. The operator is defined for these types in the 2008 version of ieee.numeric_std, which is why I believe the Vivado simulator is using the 2008 version of the IEEE library.
Why does this matter? In principle, the tool needs to use the correct libraries for the specified language version. But the big problem for me is that that this results in collisions at compile time because I have this operator (and others) defined for these data types (and others) in my own packages for use in VHDL-2002, where they do not exist in the IEEE library. This overlap results in the inability of the compiler to resolve the operators, which means I cannot simulate any of my HDL that uses these packages! This is a big deal.
If I am mistaken, please correct me. If not, then please look into this and get the Vivado simulator fixed.
11-17-2016 08:00 PM
I am able to reproduce the issue and debugging the same.
I will keep you posted with the updates.
11-17-2016 11:01 PM
I filed a bug report for the factory to fix this issue in future release.
The bug number associated with this issue is CR-964258.
11-18-2016 02:02 AM
This issue is not seen in 2016.2 as you mentioned and is the intended change from 2016.3
11-18-2016 09:57 AM
Thank for looking into this. I was able verify that the -93_mode switch does allow xvhdl to compile my non-2008 HDL. However, I still have a couple of issues.
First, UG900 that you referenced clearly states on page 168 that "The default mode for xvhdl is to compile in VHDL 93 mode. To compile a file with VHDL 2008 mode, you need to pass -2008 switch to xvhdl." This is contrary to what you said that XSIM allows mixing without a switch. I could understand if it allowed mixing based on the file type. For example, XSIM would use 2008 libraries for files specified as type "VHDL 2008", and use 93 libraries for files specified as type "VHDL". That would make good sense. But that is obviously not how XSIM behaves as demonstrated by my problem. So there seems to be a conflict here. Can you please clarify?
Second, while the -93_mode switch did solve the first xvhdl problem, xvhdl does not compile the Xilinx IP cores (the simulation settings are configured for mixed language), and xelab now stops on the following error: "osc_tb.vdb needs to be re-saved since std.standard changed". This exact same project simulates fine in 20016.2.
11-19-2016 09:18 AM
Good luck with this
VHDL is not native to Xilinx any more
Its a pity that this simple bug has been re categorised as expected behaviour.
11-27-2016 11:30 PM
1) Yes, this is a documentation issue. I will file a bug report on UG-900 and let you know the details.
2) Regarding your second point, if you are compiling any design with ‘-93_mode’, all your VHDL design files including those going in compile_simlib need to be compiled with ‘-93_mode’. At present we don’t have that provision to pass flag in compile_simlib. I will check with the factory on this and update you.
11-29-2016 01:13 AM
I filed a bug report CR-964748 to fix the documentation.
12-16-2016 07:50 AM
@vijayak, the more I think about this the more disappointed I am in the decision to "mix" VHDL 93 and 2008 in the Vivado simulator. As I understand it, this means that if a single file in the design is incompatible with 2008 then the entire design must be restricted to 93 (-93_mode), which means that 2008 files cannot be included in the design. For some designs this may work just fine. But what if I have some files that are incompatible with 2008, and I want to add files from a third party (or develop my own) that require 2008? In that case, the Vivado simulator will not work! The Vivado simulator really should treat each file as its specified type (93, 2008) so that it can properly support mixed VHDL file types in a design.
Will you please communicate my feedback to the factory? I sincerely hope they will change this behavior.
12-16-2016 11:01 AM
You might have to wait a while.
Experience shows that Verilog is the preferred HDL language for Xilinx