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Registered: ‎08-30-2017

Vivado 2016.4 Simulating Core Containers for Active-HDL / Export Scripts problems

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Hi,

 

I am attempting to simulate a design from Vivado 2016.4 to Active-HDL.  I have tried it two ways:

 

1. Using the GUI and Run Simulation.  I get an error in the compile.log about a missing source file:

 

# Error: VCP1010 Cannot find source file: C:/path/to/example/simulation/fifo_generator_vlog_beh.v

 

Where 'C:/path/to/example' matches the name of any of the .xcix core container files found in the project.  The .xcix isn't included in this path, it tries to reference the file as if the .xcix is a directory, so I assume this is a bug with using the container file format in Vivado.  I don't want to turn off packing in the core containers because there are over a hundred IP cores in use in the overall design.  The Vivado simulator is failing to generate the IP user files and reference them when creating the active-HDL script.

 

2. Using the export_simulation approach.  In this case I get a script that simply does not work in Active-HDL (10.4a).  I'm on Windows 10 so I have to skip the bash shell script, but I was able to review it and see that the main point is to make sure I have my library.cfg file in the directory and then run compile.do.  So I copy the library.cfg, launch Active-HDL, change to the directory, and type "source compile.do".  

 

The vlib commands all give "Warning: Cannot create library", the vmap commands all give "AMAP: Error: Library: [such-and-such] does not exist." and the vcom lines give me "Error: DO_001 in file compile.do line X."

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ryanbales
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Registered: ‎12-01-2017

Doc,

 

I've also encountered several problems when using Active-HDL and Vivado.  Unfortunately, Aldec and Xilinx don't seem to work together to streamline the process.  I prefer to drive the simulation within Active-HDL, rather than setting Active-HDL as the default simulator inside Vivado.  I'm also running Windows 10.

 

The following approach has worked well for me; you might be running into some of the same bugs that I did.  Unfortunately it's a pretty manual process.  In step 3, I run the export_simulation command for each IP core individually, and edit some of the automatically generated files.  I can get away with that since I only have a handful of IP cores.  This is probably less attractive if you have over 100 cores, but someone more adept than I at scripting might know of a way to automate the process.  If so, I'd be very interested.... 

 

Most of the problems I've seen are due to relative paths in the IP cores' compile.do scripts being relative to the wrong directory.  If there were a way to have the TCL commands generate scripts with absolute path names, that would help a lot.

 

  1. Generate simulation libraries in Vivado

compile_simlib -force -language vhdl -dir {C:/annapolis/compile_simlib} -simulator active_hdl -simulator_exec_path {C:/Aldec/Active-HDL-10.4-x64/BIN} -library all -family  all

 

  1. Attach the libraries (globally) by opening Aldec. Do NOT open a workspace.  Go to Library->Attach Library, and select each of the .lib files (secureip, unifast, unimacro, unisim, xpm)

 

  1. In Vivado, export the simulation library for each IP core. Enter the following in the TCL Console

export_simulation -directory "C:/annapolis/my_ip" -simulator "activehdl" –absolute_path -lib_map_path "C:/annapolis/compile_simlib"  -of_objects [get_files your_ip_name.xci]

 

 4.  In a command or Powershell console, navigate to the export directory from Step 3, and run the *.sh file generated for each IP core

./your_ip_name.sh –lib_map_path “C:\annapolis\compile_simlib\”

 

 5.  In Aldec, open library menu. Change xpm library (from Xilinx) to R/W instead of R/O (Read Only).

 

 6.  Add compile.do file for IP core to Active-HDL project (be sure to de-select Make Local Copy!) and execute.

  1.    Seems to be problem in compile.do with the path to fifo_generator_vlog_beh.v. Path in compile.do might assume a different starting point?
  2.    Manually edit compile.do file to use full paths
    1. "C:/annapolis/wsku_vpx3u_iope_sram_1p34p0/examples/iope/ak_drfm_4TG/synth/ak_drfm_4TG.srcs/sources_1/ip/fifo_256bx256…

For certain types of IP cores, I encountered the error:

  1. Error: COMP96_0196: ../../../../.../axi_utils_v2_0_vh_rfs.vhd : (3811, 170): Expression must be locally static if the entity name list denotes an entity interface, architecture body or configuration declaration.
  2. To resolve, add –relax to vcom line in compile.do:
    1. vcom -work axi_utils_v2_0_3 -relax -93 \

 

For certain types of IP cores, I encountered the error:

  1. vlog -work xil_defaultlib "glbl.v" “Cannot find source file glbl.v
  2. Seems to be another relative path problem.  Manually edit compile.do line 31 to:
  3. vlog -work xil_defaultlib "C:/Xilinx/Vivado/2016.4/data/verilog/src/glbl.v"
  4. Finishes compilation and components appear in xpm library, vcomponents unit.
  5. Does seem to compile encrypted units okay.

 6. In the files that use these IP cores, add the following lines at the top.

         library xil_defaultlib;

         use xil_defaultlib.all;

 

 In Active-HDL, check the option:

Simulation->Preferences->Compilation->VHDL Compiler -> check Relax LRM Requirements

 

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1 Reply
ryanbales
Observer
Observer
2,682 Views
Registered: ‎12-01-2017

Doc,

 

I've also encountered several problems when using Active-HDL and Vivado.  Unfortunately, Aldec and Xilinx don't seem to work together to streamline the process.  I prefer to drive the simulation within Active-HDL, rather than setting Active-HDL as the default simulator inside Vivado.  I'm also running Windows 10.

 

The following approach has worked well for me; you might be running into some of the same bugs that I did.  Unfortunately it's a pretty manual process.  In step 3, I run the export_simulation command for each IP core individually, and edit some of the automatically generated files.  I can get away with that since I only have a handful of IP cores.  This is probably less attractive if you have over 100 cores, but someone more adept than I at scripting might know of a way to automate the process.  If so, I'd be very interested.... 

 

Most of the problems I've seen are due to relative paths in the IP cores' compile.do scripts being relative to the wrong directory.  If there were a way to have the TCL commands generate scripts with absolute path names, that would help a lot.

 

  1. Generate simulation libraries in Vivado

compile_simlib -force -language vhdl -dir {C:/annapolis/compile_simlib} -simulator active_hdl -simulator_exec_path {C:/Aldec/Active-HDL-10.4-x64/BIN} -library all -family  all

 

  1. Attach the libraries (globally) by opening Aldec. Do NOT open a workspace.  Go to Library->Attach Library, and select each of the .lib files (secureip, unifast, unimacro, unisim, xpm)

 

  1. In Vivado, export the simulation library for each IP core. Enter the following in the TCL Console

export_simulation -directory "C:/annapolis/my_ip" -simulator "activehdl" –absolute_path -lib_map_path "C:/annapolis/compile_simlib"  -of_objects [get_files your_ip_name.xci]

 

 4.  In a command or Powershell console, navigate to the export directory from Step 3, and run the *.sh file generated for each IP core

./your_ip_name.sh –lib_map_path “C:\annapolis\compile_simlib\”

 

 5.  In Aldec, open library menu. Change xpm library (from Xilinx) to R/W instead of R/O (Read Only).

 

 6.  Add compile.do file for IP core to Active-HDL project (be sure to de-select Make Local Copy!) and execute.

  1.    Seems to be problem in compile.do with the path to fifo_generator_vlog_beh.v. Path in compile.do might assume a different starting point?
  2.    Manually edit compile.do file to use full paths
    1. "C:/annapolis/wsku_vpx3u_iope_sram_1p34p0/examples/iope/ak_drfm_4TG/synth/ak_drfm_4TG.srcs/sources_1/ip/fifo_256bx256…

For certain types of IP cores, I encountered the error:

  1. Error: COMP96_0196: ../../../../.../axi_utils_v2_0_vh_rfs.vhd : (3811, 170): Expression must be locally static if the entity name list denotes an entity interface, architecture body or configuration declaration.
  2. To resolve, add –relax to vcom line in compile.do:
    1. vcom -work axi_utils_v2_0_3 -relax -93 \

 

For certain types of IP cores, I encountered the error:

  1. vlog -work xil_defaultlib "glbl.v" “Cannot find source file glbl.v
  2. Seems to be another relative path problem.  Manually edit compile.do line 31 to:
  3. vlog -work xil_defaultlib "C:/Xilinx/Vivado/2016.4/data/verilog/src/glbl.v"
  4. Finishes compilation and components appear in xpm library, vcomponents unit.
  5. Does seem to compile encrypted units okay.

 6. In the files that use these IP cores, add the following lines at the top.

         library xil_defaultlib;

         use xil_defaultlib.all;

 

 In Active-HDL, check the option:

Simulation->Preferences->Compilation->VHDL Compiler -> check Relax LRM Requirements

 

View solution in original post