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Explorer
Explorer
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Registered: ‎01-12-2009

Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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In a fairly large simulation I am getting ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. I do not know what statement is causing the fault.

 

I have reproduced the error and partially reproduced the stack trace below and attached the full stack trace as a text file.

 

Can you isolate the source of the code defect from the stack trace, or do I have to isolate the actual code that is causing the fault for you to be able to locate the code error?

 

Ian Lewis

www.mstarlabs.com

 

 

ComMsgMgrException: I/O error while reading file I:/Tools/Xilinx/Vivado/2017.2/data/msg/xsimverific.msg

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Printing stacktrace...

[0] (KiUserExceptionDispatcher+0x3a) [0x7ff829ac9c8a]
[1] (ComMsgMgrFile::getVersionNo+0x941) [0x7fffed3a0cd1]
[2] (ComMsgMgrFile::findMsgEntryByKey+0x40) [0x7fffed39f940]
[3] (ComMsgMgrFile::getMsgEntry+0x413) [0x7fffed39fe83]
[4] (HUTTextTable::addRow_+0x89d1) [0x7fffed3bb1d1]
[5] (ComMsgMgrInstance::wasSuppressedAtEndOfCreation+0x5142) [0x7fffed3cfca2]
[6] (ComMsgMgrInstance::ComMsgMgrInstance+0x87) [0x7fffed3c61c7]
[7] (ISIMC::Options::parseVlogcompCommandLine+0x2cba4) [0x7ff631f78c34]
<snip>
[1008] (Verific::VhdlDesignUnit::VhdlDesignUnit+0xbb) [0x7fffbdf4f49b]
[1009] (Verific::VhdlPrimaryUnit::VhdlPrimaryUnit+0x34) [0x7fffbdf52114]
[1010] (Verific::VhdlPackageDecl::VhdlPackageDecl+0x30) [0x7fffbdf51a00]
[1011] (Verific::VhdlTreeNode::CreateObject+0x6ef) [0x7fffbdf5bfdf]
[1012] (Verific::vhdl_file::Restore+0x47c) [0x7fffbdf5eeac]
[1013] (Verific::VhdlLibrary::GetPrimUnit+0x20f) [0x7fffbe031c8f]
[1014] (Verific::VhdlScope::RegisterDependencies+0x7c8) [0x7fffbdf5e408]
[1015] (Verific::VhdlScope::RegisterDependencies+0x36e) [0x7fffbdf5dfae]
[1016] (Verific::VhdlScope::VhdlScope+0x6f) [0x7fffbdf52b9f]
[1017] (Verific::VhdlTreeNode::RestoreScopePtr+0x6c) [0x7fffbdf5f95c]
[1018] (Verific::VhdlDesignUnit::VhdlDesignUnit+0xbb) [0x7fffbdf4f49b]
[1019] (Verific::VhdlPrimaryUnit::VhdlPrimaryUnit+0x34) [0x7fffbdf52114]

Done
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:33 . Memory (MB): peak = 1097.078 ; gain = 11.680
INFO: [USF-XSim-69] 'elaborate' step finished in '33' seconds
INFO: [USF-XSim-99] Step results log file:'H:/Eng/MVhdl/Env/Vivado/Sim1/Sim1.sim/sim_1/behav/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'H:/Eng/MVhdl/Env/Vivado/Sim1/Sim1.sim/sim_1/behav/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:01:29 . Memory (MB): peak = 1097.078 ; gain = 11.680
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

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Moderator
Moderator
5,365 Views
Registered: ‎09-15-2016

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Hi @ilewis,

 

I was able to reproduce the issue and filed CR-985318 for this issue to get it addressed in future releases of tool.

 

Thanks & Regards,
Sravanthi B
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Sravanthi B
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13 Replies
Moderator
Moderator
3,821 Views
Registered: ‎09-15-2016

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Hi @ilewis

 

Here are couple of things to check:

1) Since the crash happens in the elaborate step of the simulation, hence please check the elaborate.log located in the <project_dir>.sim/sim_1/behav .See if you  you find any helpful error which can help you to narrow down to particular source of code causing crash.

2) Try recreating the project from the scratch and see if it helps.

 

Which OS you are using? Make sure you are using supported OS for Vivado 2017.2. Refer the below link, page 8 for information on this:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug973-vivado-release-notes-install-license.pdf

 

Hope this helps.

 

Regards

Rohit

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Regards
Rohit
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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Hi @ilewis,

 

What is the OS you are working up on?
Can you please share the elaborate.log file located in H:/Eng/MVhdl/Env/Vivado/Sim1/Sim1.sim/sim_1/behav/elaborate.log
Also, Please share the archived design or the part of the code which is causing the issue.
If possible try simulating the same design on any different machine.

 

Thanks & Regards,
Sravanthi B

Thanks & Regards,
Sravanthi B
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Explorer
Explorer
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Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Hello Sravanthi, Rohit,

 

I am running on Win10 Pro, Anniversary Update: Version 1607 (OS Build: 14393.1593).

 

I have attached the elaborate.log file as well as reproduced it below. It contains nothing useful.

 

I have not yet isolated the source of the failure. I cannot post the full design.

 

I will see whether I can isolate the code that is causing the fault, but I do not think it is going to be easy to find.

 

This is clearly a bug. Nothing should cause a run-time fault. I was hoping the stack trace would tell you something so that I would not have to locate where the error is happening.

 

Note: The exact same design (same source modules) simulates without any problems in ModelSim. I am trying to move our simulations from ModelSim to Vivado for new work.

 

Ian Lewis

www.mstarlabs.com

 

Content of elaborate.log:

====================

Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: I:/Tools/Xilinx/Vivado/2017.2/bin/unwrapped/win64.o/xelab.exe -wto 16aec317eb264ab2bebb86b96f92414c --debug all --mt 2 -L MVhdl -L XilinxCoreLib -L MXVhdl -L Test -L TestXil -L secureip --snapshot TestSynchPulse_behav Test.TestSynchPulse -log elaborate.log
Using 2 slave threads.
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Explorer
Explorer
3,733 Views
Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Ok. Here is a highly reduced example of the crash I am seeing.


There is no code at all involved in the problem. The problem is apparently related to relationships between packages in VHDL.

 

The crash seems 100% reproducible. I get it on every run with this very simple example.

 

I have found no work around and I have yet to figure out how we can move forward with our simulation,

 

Let me know whether you can reproduce the failure. If you can, please file a CR. And, if you can see a workaround that avoids the bug, let me know what it is.

 

Ian Lewis

www.mstarlabs.com

 

 

Explorer
Explorer
3,662 Views
Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Can someone from Xilinx please verify this error and file a CR?

 

This is defect is seriously in the way of our using the Vivado Simulator in place of the ModelSim simulator.


Ian Lewis

www.mstarlabs.com

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Explorer
Explorer
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Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Hello?

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Moderator
Moderator
5,366 Views
Registered: ‎09-15-2016

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Hi @ilewis,

 

I was able to reproduce the issue and filed CR-985318 for this issue to get it addressed in future releases of tool.

 

Thanks & Regards,
Sravanthi B
---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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Visitor aspenlogic
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Registered: ‎08-01-2014

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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I had the exact same problem as you. Check your file(s) for non-ascii, non-printing, illegal characters. By accident, I found that EMACS choked on some characters (which appeared as Chinese glyphs) embedded in the middle of a VHDL comment block that originated in a copy+paste operation from a PDF datasheet. I suspect they are Unicode characters that did not translate well in the paste operation! After removing these, the Vivado VHDL elaboration succeeded and I no longer received the access violation message. Shame on the Vivado XSIM/XELAB parsers for choking on them too and in a comment no less. (Even stranger that the synthesis and simulation parsers must be different...) Aspen Logic, Inc. by: Timothy R Davis, President Logic Design Done Logically at https://aspenlogic.com
ASPEN LOGIC, INC.
By: Timothy R Davis, President
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Visitor seanlittle
Visitor
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Registered: ‎11-06-2018

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Looks like it has been a couple of years since you submitted this problem. Did you ever get a resolution? I appear to be having the same issue in 2018.2.

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Explorer
Explorer
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Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Unfortunately, because of this issue and several others, I gave up on using the Vivado simulator and I have not tried again for at least a year, probably longer.

I am not currently working on any HDL projects. But, I expect to begin some new work some time in the next few months. When I do, I will again see if I can make the Vivado simulator work for our purposes.

If my trivial source module relationship test still crashes, in 2018.2, that is not a good sign for my succeeding.

Ian Lewis
www.mstarlabs.com

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Explorer
Explorer
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Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Can anyone from Xilinx say whether CR-985318 has been investigated or fixed?

Ian Lewis
www.mstarlabs.com

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Visitor seanlittle
Visitor
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Registered: ‎11-06-2018

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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I was mistaken. My crash is caused by a mixed language sim that has a default clocking block in the top level testbench. I did attempt to run your sim, Ian, in Vivado 2018.2. There is no longer a crash, but the simulation doesn't elaborate either. Vivado complains about some kind of permissions issue, which makes no sense since when I comment out the line of code that you flagged, the project is able to elaborate successfully. I didn't investigate further since this is different from my issue. Good luck.

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Explorer
Explorer
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Registered: ‎01-12-2009

Re: Vivado 2017.2: ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

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Thank you for the update, seanlittle. I am glad that at least it does not crash any more. - Ian

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