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Anonymous
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Vivado 2017.2 NCSIM problem

Hello,

 

I have a design in Ultra-scale which contains some HLS genertaed IPs. When I simulate with XSIM, everything work fine.

 

When I simulate with NCSIM (version 15.20.026) using same test bench, simulation is not correct. There is no error in simulation flow but during the first register access from test bench, interconnect give decode error.

 

What might be the problem? Am I using the correct tools and versions?

 

Regards

Anoop

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

You can find list of supported document in the installation guide
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug973-vivado-release-notes-install-license.pdf

I suggest you recommend that you can use the Vivado run_simulation -scripts_only option to dump compile scripts and see how to set up the libraries . How are you invoking NSIM through HLS/Vivado or in NSIM compiling your code

Thanks and Regards
Balkrishan
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Anonymous
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