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Anonymous
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Vivado 2017.2 simulation issue with NCSIM

Hi all,

 

I created a block design in Vivado 2017.2 targeting Kintex Ultra-Scale. The design is pretty big consists of 7 interconnects, seven micro blazes, some HLS IPs etc. During each stages of block design creation, I simulated it with NCSIM (version 15.20.026, in GUI) and wrote block design to a TCL file. After completing the block I  ran the simulation again. Simulation was OK and I wrote the final block design as a TCL file.

 

Then I changed some project settings related to synthesis and implementation , generated output product. After that I removed block design from the project (deleted all project local files). Closed the project.

 

Later, when I opened the project, source the block diagram and ran simulation, first register access is giving interconnect decode error. The same behavior is with all the intermediate tcl files. 

 

Is there any problem with Vivado 2017.2 while writing or sourcing block design? (I forgot to save .BD file when it was working)

 

Block design validation did not gave any errors but some warnings only. Since the files have some confidentiality issues, I cannot share it. Sorry.

 

Test case only contains some register access by forcing the AXI port of a master from test bench. ( Test bench and test cases are proven and has been used in many project )

 

Regards

anoop

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2 Replies
Anonymous
Not applicable
1,000 Views

Hi 

 

 

 

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Anonymous
Not applicable
951 Views

Hi all,

(balkris,)

 

I found the reason for interconnect decode error. It seems a tool issue. I think You still have some  flaws in simulation flow.

 

There is a mig in the design(4GB). Microblaze have only 2GB access to mig. Therefore the interconnect to which microblaze is connected will automatically infer an MMU. When vivado sources tcl file and genertae PRJ.ip_user_files, this MMU RTL is generated with different parameters when compared to the situation of no decode error. 

(PRJ.ip_user_files\bd\rx_subsystem\ip\rx_subsystem_s00_mmu_0\sim\rx_subsystem_s00_mmu_0.v)

 

parameter comparison

 

Working case

axi_mmu_v2_1_11_top #(

.C_NUM_RANGES(1),
.C_BASE_ADDR('H0000000081000000),
.C_RANGE_SIZE('H00000014),

.C_M_AXI_SUPPORTS_WRITE('H0000000000000001),
.C_M_AXI_SUPPORTS_READ('H0000000000000001)

 

not working case

axi_mmu_v2_1_11_top #(

.C_NUM_RANGES(4),
.C_BASE_ADDR('H0000000084080000000000008404000000000000840300000000000084010000),
.C_RANGE_SIZE('H00000013000000110000001000000010),

.C_M_AXI_SUPPORTS_WRITE('B1111),
.C_M_AXI_SUPPORTS_READ('B1111)

 

 

When I copied the working case rx_subsystem_s00_mmu_0.v file , it worked.

When I un-mapped mig from microblaze(to remove MMU), then also it worked. 

 

But both these solution seems to be temporary. I request Xilinx to provide some advice and a solution.

 

Regards

Anoop

 

 

 

Regards

Anoop

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