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Observer
Observer
4,133 Views
Registered: ‎03-10-2017

Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

With Vivado 2017.3 and Modelsim 10.7, I get the following warning when I try compiling the libraries with compile_simlib:

INFO: [Vivado 12-5496] Finding simulator executables and checking version...
WARNING: [Vivado 12-5495] Detected incompatible modelsim simulator installation version '10.7'! The supported simulator version for the current Vivado release is '10.6b'.
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...

note that 10.7 > 10.6b, so according to the Xilinx documentation it should be supported (10.6b is the minimum requirement, not an exact match).

 

Then I get the following error while the individual libraries are being compiled (this is the only error):

Compiling verilog library 'ldpc_v1_0_0'...
==============================================================================
BEGIN_COMPILATION_MESSAGES(modelsim:verilog:ldpc_v1_0_0)
Model Technology ModelSim DE vmap 10.7 Lib Mapping Utility 2017.12 Dec  6 2017
vmap ldpc_v1_0_0 /nfs/fpgadev/ZDrive/XSimLib_v2017.3_v10.7/XSimLib_v2017.3_v_10/ldpc_v1_0_0
Modifying modelsim.ini
Model Technology ModelSim DE vlog 10.7 Compiler 2017.12 Dec  6 2017
Start time: 10:27:31 on Jan 09,2018
vlog -32 -L fec_5g_common_v1_0_0 -L ldpc_v1_0_0 "+incdir+/nfs/fpgadev/ZDrive/XSimLib_v2017.3_v10.7/XSimLib_v2017.3_v_10/.cxl.ip/incl" -sv -work ldpc_v1_0_0 -f /nfs/fpgadev/ZDrive/XSimLib_v2017.3_v10.7/XSimLib_v2017.3_v_10/ldpc_v1_0_0/.cxl.systemverilog.ldpc_v1_0_0.ld
pc_v1_0_0.lin64.cmf
** Warning: /nfs/fpgadev/Xilinx/Vivado/2017.3/data/ip/xilinx/ldpc_v1_0/hdl/ldpc_v1_0_rfs.sv(64): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
[ . . . ]
** Error: /nfs/fpgadev/Xilinx/Vivado/2017.3/data/ip/xilinx/ldpc_v1_0/hdl/ldpc_v1_0_rfs.sv(64): in protected region
** Error: /nfs/fpgadev/Xilinx/Vivado/2017.3/data/ip/xilinx/ldpc_v1_0/hdl/ldpc_v1_0_rfs.sv(64): in protected region
** Error: /nfs/fpgadev/Xilinx/Vivado/2017.3/data/ip/xilinx/ldpc_v1_0/hdl/ldpc_v1_0_rfs.sv(64): in protected region
** Warning: /nfs/fpgadev/Xilinx/Vivado/2017.3/data/ip/xilinx/ldpc_v1_0/hdl/ldpc_v1_0_rfs.sv(64): (vlog-2583) [SVCHK] - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.
[ . . . ]

The incompatibility warning and errors were not present when I compiled the libraries for Vivado 2017.2 and Modelsim 10.7. Everything compiled and worked.

 

My questions are:

  1. Is there a workaround for this issue without having to go backward in Modelsim?
  2. Does 2017.4 have the same issue, or is it fixed?
  3. If we don't use the ldpc library, can I simply ignore this warning/error? are there other issues that caused Xilinx to add the Warning in 2017.3?
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6 Replies
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Observer
Observer
4,087 Views
Registered: ‎03-10-2017

Re: Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

I probably should have mentioned previous steps to get to this point:

 

Modelsim 10.7 gives other error while running compile_simlib due to Vivado 2017.2 and 2017.3 adding the '-novopt' option while trying to compile the libraries (which has been deprecated in previous versions of modelsim and changed to an error in 10.7).

 

To get around these, I had to remove the -novopt option from the launched command:

	config_compile_simlib -cfgopt {modelsim.verilog.axi_bfm:-quiet}
	config_compile_simlib -cfgopt {modelsim.verilog.ieee:-quiet}
	config_compile_simlib -cfgopt {modelsim.verilog.simprim:-source +define+XIL_TIMING}
	config_compile_simlib -cfgopt {modelsim.verilog.std:-quiet}
	config_compile_simlib -cfgopt {modelsim.verilog.synopsys:-quiet}
	config_compile_simlib -cfgopt {modelsim.verilog.unisim:-source}
	config_compile_simlib -cfgopt {modelsim.verilog.vl:-quiet}
	config_compile_simlib -cfgopt {modelsim.vhdl.axi_bfm:-93 -quiet}
	config_compile_simlib -cfgopt {modelsim.vhdl.ieee:-93 -quiet}
	config_compile_simlib -cfgopt {modelsim.vhdl.simprim:-source -93}
	config_compile_simlib -cfgopt {modelsim.vhdl.std:-93 -quiet}
	config_compile_simlib -cfgopt {modelsim.vhdl.synopsys:-93 -quiet}
	config_compile_simlib -cfgopt {modelsim.vhdl.unisim:-source -93}
	config_compile_simlib -cfgopt {modelsim.vhdl.vl:-93 -quiet}

. . . but this still does not fix the issue for secureIP library which does not have a library entry.  For that, I had to downgrade the 12110 error to a warning (which is allowed) . . . in the modelsim.ini file I added it to the suppress list:

suppress = 8780,12110 ;an explanation can be had by running: verror 8780

After doing all this, everything works fine for 2017.2, but I get the error described in the original post for 2017.3

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Xilinx Employee
Xilinx Employee
4,010 Views
Registered: ‎07-16-2008

Re: Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

I gave it a try with Modelsim SE 10.7 and didn't encounter this error.

What if you go to the ldpc directory and manually run the vlog command?

 

cd /nfs/fpgadev/ZDrive/XSimLib_v2017.3_v10.7/XSimLib_v2017.3_v_10/ldpc_v1_0_0

vlog -32 -L fec_5g_common_v1_0_0 -L ldpc_v1_0_0 "+incdir+/nfs/fpgadev/ZDrive/XSimLib_v2017.3_v10.7/XSimLib_v2017.3_v_10/.cxl.ip/incl" -sv -work ldpc_v1_0_0 -f /nfs/fpgadev/ZDrive/XSimLib_v2017.3_v10.7/XSimLib_v2017.3_v_10/ldpc_v1_0_0/.cxl.systemverilog.ldpc_v1_0_0.ld
pc_v1_0_0.lin64.cmf

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Visitor
Visitor
3,911 Views
Registered: ‎01-29-2018

Re: Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

I had a similar problem with Modelsim PE 10.7 and Vivado 2017.4. I found out, that there is a hidden simulator option for the "compile_simlib" command solving the problem.

 

Starting the generation of the simulation libraries with the Vivado GUI results in follwing tcl command line:

compile_simlib -simulator modelsim -simulator_exec_path {C:/modelsim_pe_10.7/win32pe} -family all -language all -library all -dir {C:/Xilinx/SimLibs/2017.4/modelsim_pe_10.7} -32bit

This results in the "-novopt" error.

 

By searching the string "-novopt" within the Vivado install folder, I found following settings file:

C:\Xilinx\Vivado\2017.4\data\parts\xilinx\compxlib\config_compile_simlib.acd

Within this file I found settings for "modelsim" and for "mti_pe", where the "-novopt" switch was removed for UNISIM, SIMPRIM an XPM libraries.

 

So I changed "modelsim" to "mti_pe" and all libraries where compiled sucessfully:

compile_simlib -simulator mti_pe -simulator_exec_path {C:/modelsim_pe_10.7/win32pe} -family all -language all -library all -dir {C:/Xilinx/SimLibs/2017.4/modelsim_pe_10.7} -32bit

 

Unfortunatly the option "mti_pe" is hidden and not presented by the GUI nor the help.

 

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Visitor
Visitor
3,890 Views
Registered: ‎03-25-2015

Re: Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

I had the same issue. I am using Vivado 2016.2 and this had the same issues with Modelsim version 10.7.

I had an error message on starting simulation scripts to say that the libraries needed to be recompiled because the  ieee.std_logic_1164 library had changed. This lead to having issues with the recompilation process and to this forum.

 

I had to modify the following files:

Vivado\2016.2\ids_lite\ISE\data\compxlib_defaults.acd

Vivado\2016.2\data\parts\xilinx\compxlib\compxlib_defaults.acd

Vivado\2016.2\data\parts\xilinx\compxlib\config_compile_simlib.acd

Then start Vivado and recompile the Modelsim libraries before it would work.

 

I found that before this, the unisim library was shown in Modelsim as mapped but empty.

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Newbie
Newbie
1,614 Views
Registered: ‎12-11-2018

Re: Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

I'm getting this error for 2018.3. After adding: "suppress = 8780,12110 ;an explanation can be had by running: verror 8780" to init file, the error still occurs. It appears to occur when compiling Xilinx IP, in this case a clock wizzard.

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Observer
Observer
232 Views
Registered: ‎01-02-2019

Re: Vivado 2017.3 IP Libraries have an issue when compiling for Modelsim 10.7 with compile_simlib

Hi All,

I tried to compile Questa 2020_1 libraries with Vivado 2019.1 and got the following error:

WARNING: [Vivado 12-5495] Detected incompatible questasim simulator installation version '2020.1'! The supported simulator version for the current Vivado release is '10.7c'.

 

I used the command:

compile_simlib -simulator questa -simulator_exec_path {/tools/mentor/2020_1/questasim/bin} -dir {/tools/xilinx/Vivado/2019.1/compile_simlibs_questa_2020_1}

 

Problem was solved when I re-installed Questa with the following products:

Questa SIM 64-bit, GCC 64-bit and Register Assistant UVM. 

Before the re-installation GCC wasn't installed.

 

Gal

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