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Observer
Observer
791 Views
Registered: ‎01-29-2014

Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

I have a strange version issue with simulating postroute netlist in Vivado. The same compilation script works in 2016.4 but not in 2018.3. How do I resolve this situation? I want to use 2018.3 because 2016.4/2017.4 do not support external signal naming in VHDL-2008 but now I am not even able to compile the files in 2018.3. Its so frustrating :(

 

I compile the Verilog netlist into a library and then use the library in my VHDL toplevel testbench.

My project files are:

vlog.prj: verilog GATE_LIB postroute.v

vhdl.prj: vhdl2008 xil_defaultlib ./tb.vhd

 

In tb.vhd, I have

LIBRARY GATE_LIB;

USE GATE_LIB.ALL;

DUT: ENTITY GATE_LIB.Top

 

The commands are:

xvlog -m64 --relax -prj vlog.prj

xvhdl --2008 --relax -L GATE_LIB -prj vhdl.prj

The last command fails with VRFC 10-2987 'top' is not compiled in library 'GATE_LIB' even though the xvlog command shows Top was analyzed into GATE_LIB.

 

 

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4 Replies
Highlighted
Observer
Observer
757 Views
Registered: ‎01-29-2014

Re: Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

My update:

I put in a component declaration for the Verilog module Top and replaced the USE entity.GATE_LIB.Top from the VHDL instantiation with just DUT:Top and now it works in 2018.3.

It seems strange that 2016.4 works with the entity instantiation type.

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Highlighted
Observer
Observer
654 Views
Registered: ‎08-13-2014

Re: Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

Hi,

i have the same strange behavior and could fix it with the additional component declaration. Come on Xilinx Support it's still in Vivado 2019.1. ... I'm so tired of all the pitfalls i step into ...

 

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Adventurer
Adventurer
108 Views
Registered: ‎04-01-2019

Re: Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

so agree. Its so frustrating. I had a design that worked fine. Just saved it with a different name and it get this error. Nothing has changed from the working version!!

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Adventurer
Adventurer
79 Views
Registered: ‎01-27-2008

Re: Vivado 2018.3 VRFC 10-2987 (cannot load compiled Verilog netlist in VHDL testbench) - Same works in 2016.4

I had something similar

INFO: [VRFC 10-163] Analyzing VHDL file "<some FIR filt name>.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity '<some FIR filt name>'
ERROR: [VRFC 10-2987] '<some FIR filt name>' is not compiled in library 'xil_defaultlib' [<some FIR filt name>.vhd:125]
ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [<some FIR filt name>.vhd:76]
INFO: [VRFC 10-3070] VHDL file '<some FIR filt name>.vhd' ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '4' seconds

The way I was able to resolve this was to recreate the testbench new project. I swapped IPs during the project and they had similar names. Perhaps XSIM gets confused?

That's why running sim and synth from scripts is best. It was simple but unintuitive, to fix this bug in their tool.

-Jerry

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