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Observer app076
Observer
176 Views
Registered: ‎01-29-2014

Vivado 2019.1 static elaboration fails without any error message

I have a design that elaborates fine with Vivado 2018.3 but fails with no error message with Vivado 2019.1. The only message provided by 2019.1 version is 'XSIM 43-3322 Static elaboration of top level Verilog design unit(s) in library failed'.  There is no other error to indicate what may be happening.

How do I debug this?

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Xilinx Employee
Xilinx Employee
152 Views
Registered: ‎07-16-2008

回复: Vivado 2019.1 static elaboration fails without any error message

Any more information from the xelab.log? Also try to enable '-v 1' option of xelab and review the phase it fails at.

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