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sajjad_b
Visitor
Visitor
2,042 Views
Registered: ‎06-10-2018

Vivado HLS RTL/Cosimulation Fail

Hi
I have problem in Vivado HLS
I'm developing an ipcore that the input is AXI-Stream and the output is AXI-Stream too.
There is no problem in C Syntheseis, and also it works well in C Simulation.
But RTL/Cosimulation is failing.

My Top Function is like this : 

void CT(point_in SetA[2 * M], point_out Centers[M]){

#pragma HLS INTERFACE axis register both port=SetA
#pragma HLS INTERFACE axis register both port=Centers

...

}

 

This is the console message when I try to run RTL/Cosimulation:

...
Starting static elaboration
ERROR: [VRFC 10-147] xbip_pipe_v3_0_5.xbip_pipe_v3_0_5_viv_comp failed to restore
ERROR: [VRFC 10-213] Registering Dependencies Error: The library 'xbip_pipe_v3_0_5' could not be found during restore
ERROR: [VRFC 10-147] floating_point_v7_1_6.floating_point_v7_1_6_viv failed to restore
ERROR: [VRFC 10-147] xbip_pipe_v3_0_5.xbip_pipe_v3_0_5_viv_comp failed to restore
ERROR: [VRFC 10-213] Registering Dependencies Error: The library 'xbip_pipe_v3_0_5' could not be found during restore
ERROR: [VRFC 10-147] floating_point_v7_1_6.floating_point_v7_1_6_viv failed to restore
ERROR: [VRFC 10-147] xbip_pipe_v3_0_5.xbip_pipe_v3_0_5_viv_comp failed to restore
ERROR: [VRFC 10-213] Registering Dependencies Error: The library 'xbip_pipe_v3_0_5' could not be found during restore
ERROR: [VRFC 10-147] floating_point_v7_1_6.floating_point_v7_1_6_viv failed to restore
WARNING: [VRFC 10-122] floating_point_v7_1_6_viv remains a black-box since it has no binding entity [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:91730]
WARNING: [VRFC 10-982] library name floating_point_v7_1_6 of instantiated unit conflicts with visible identifier [C:/Users/Dropbox/Vivado_projects/Coreset_Tree/test4/test_coreset/solution1/sim/verilog/ip/xil_defaultlib/CoresetTree_ap_fadd_3_full_dsp_32.vhd:195]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/CoresetTree/xsimk.exe" does not exist
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
command 'ap_source' returned error code
while executing
"source C:/Users/Dropbox/Vivado_projects/Coreset_Tree/test4/test_coreset/solution1/cosim.tcl"
invoked from within
"hls::main C:/Users/Dropbox/Vivado_projects/Coreset_Tree/test4/test_coreset/solution1/cosim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

5 Replies
bandi
Moderator
Moderator
1,972 Views
Registered: ‎09-15-2016

Hi @sajjad_b,

Is this issue specific to this project or is it occurring with all the designs? Can you please try running cosim on an example design and check if you are still facing the issue.

If it is specific to the project then can you please share the archived project to check this issue at our end.

Thanks & Regards,
Sravanthi B
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sajjad_b
Visitor
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1,965 Views
Registered: ‎06-10-2018

No , it is specific to this project. cosim is running well for another design.

 I shared my project.

Regards

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sajjad_b
Visitor
Visitor
1,869 Views
Registered: ‎06-10-2018

Hello bandi , any new update ?
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yaya04
Visitor
Visitor
833 Views
Registered: ‎07-30-2019

Is there any progress on this issue?

I have similar error.

In my case, my project passed 'static elaboration' but failed at 'simulation data flow analysis'.

It just terminated without any error message

WARNING: [VRFC 10-982] library name floating_point_v7_1_6 of instantiated unit conflicts with visible identifier [/home/chaeeon/chaeeon/face-mask-detection/dev/v1.1-dev/projects/YoloV2Tiny/YoloV2Tiny.dpu.fpga/hw/hls/tcl.float/proj_tiny_yolo/nexys_video/sim/verilog/ip/xil_defaultlib/yolov2tiny_ap_fcmp_1_no_dsp_32.vhd:200]
Completed static elaboration
Starting simulation data flow analysis
/opt/Xilinx/Vivado/2018.2/bin/loader: line 194: 5780 Killed "$RDI_PROG" "$@"
ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/yolov2tiny/xsimk" does not exist

Please give any idea to solve this problem.

 

Thanks for reading.

Chaeeon.

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yaya04
Visitor
Visitor
828 Views
Registered: ‎07-30-2019

I fixed the problem to increase swapfile size from 2GB to 32GB

Actually, it does not much required 32GB (it uses around 2 to 3 GB).

 

I just recognized that the memory usage suddenly increased almost full at 'simulation data flow analysis' stage

 

Thanks.

Chaeeon

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