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Explorer
Explorer
3,755 Views
Registered: ‎02-27-2018

Vivado IP catalog generates verilog code instead of VHDL

Hello,

 

I'm a starting to use Vivado 2017.4, i created a projet with target language: VHDL and simulator language: VHDL

I used the IP Catalog to instantiate an ISERDESE2, but the source file created if in Verilog.

Is it normal?

 

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Moderator
Moderator
3,742 Views
Registered: ‎03-16-2017

Hi @lebowski,

 

The Target Language setting is used to:

  • Deliver IP core synthesizable source in the desired language if both languages are available. If only one language is available, the Target Language setting is ignored and the sources are delivered in the available HDL language.
  • Deliver instantiation template in the desired language.

This Answer Record will help your query. Please have a look. https://www.xilinx.com/support/answers/51041.html

 

Regards,

hemangd

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Explorer
Explorer
3,695 Views
Registered: ‎02-27-2018

But if i the module created is in Verilog can i write a testbench in VHDL to test the module?

I don't know what types to use to declare the signals inside the components declaration

Here is the code of the module and the beginning of the testbench code

 

modulecode.png
testbench.png
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Explorer
Explorer
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Registered: ‎04-24-2014

Xilinx is currently kicking out VHDL support step by step. Even IP cores that had dual language support before are now restricted to only one language. This creates huge problems in VHDL / mixed-language simulations.

 

What is the problem of (System)Verilog components in a VHDL simulation?

 

Verilog has only a 4-valued logic stead of VHDL's 9-valued simulation model. It causes undetected errors in simulations and -- from a VHDL designers view -- produces false outputs to the VHDL testbench. As a result, a VHDL testbench author needs to restrict it's testbenches to the limited Verilog simulation model. In turn, it requires more assertions in a testbench instead letting the compiler and simulator check the correctness. There is a reason why hardware description language are static typed language. Detect errors as early as possible. This principle gets weakened by replacing VHDL simulation models with Verilog models.

 

All in all, it weakens the position of VHDL on the market because one of it's strengst compared to Verilog got eliminated. Step by step Xilinx is pushing the FPGA market which is mostly VHDL oriented into the Verilog corner.

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Scholar
Scholar
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Registered: ‎08-01-2012

All in all, it weakens the position of VHDL on the market because one of it's strengst compared to Verilog got eliminated. Step by step Xilinx is pushing the FPGA market which is mostly VHDL oriented into the Verilog corner.

 

Altera/Intel have been doing the same, but they usually provide a VHDL wrapper to mask this fact.

 

@lebowski

Mixed language is pretty common now. You map Verilog IO from components to std_logic(_vector) like you have done (annoying).

The only state you'll really miss from VHDL is the 'U' state and instead you'll get 'X'. So you wont be able to determin if there really is an error or just some uninitialised. But you might get a gotcha on a 'Z' state, as this is also used like a dont-care in verilog (as well as high impedance)

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Explorer
Explorer
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Registered: ‎04-24-2014

Intel (Altera) Quartus Prime is internally using AHDL. It's Altera own language.

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Scholar
Scholar
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Registered: ‎08-01-2012

@paebbels Yes, but at a low level (I dont think anyone actually writes any AHDL any more). I assume this is all a hangover with the way their synthesis works. Their larger IP is all being written in SV. 

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