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Visitor aimatee
Visitor
2,084 Views
Registered: ‎02-24-2018

Vivado - Post synthesis simulation

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Hi,

 

I am using Vivado 2017.1 and wrote a very simple flip flop module.

 

module simple_test(
clk, //clock
rst, //reset
row_in,
row_out
);

input clk;
input row_in;
input rst;
output row_out;

reg row_out;


always @(posedge clk or posedge rst) begin
if (rst) begin
row_out <= 1'b0;
end
else begin
row_out <= row_in;
end
end


endmodule

 

The behavioral simulation works fine, however, the post synthesis simulation showed multiple clock cycle delays from the flip flop input to the output.

 

Attached are the behavioral and post-synthesis simulation screenshots. The synthesized schematic seems fine as well.

 

What could be wrong in the setup?

 

Many Thanks!

schematic.PNG
behav_sim.PNG
post_syn_sim.PNG
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1 Solution

Accepted Solutions
Historian
Historian
2,650 Views
Registered: ‎01-23-2009

Re: Vivado - Post synthesis simulation

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In post synthesis simulation, the primitive devices used as part of the simulation (the model of the flip-flop) also model the startup delay of the FPGA. When an FPGA finishes downloading its bitstream, it stays in a built in reset state due to the "global set reset (GSR)". This holds the FPGA in the configuration state for "some time". In post-sythesis simulation this time is modeled.

 

Most likely, the 0->1 transition you are seeing at time 105 is due to the deassertion of GSR.

 

Take a look at the waveforms later in time - they will probably behave as you expect. Alternatively, keep your reset asserted for a significantly longer period of time (greater than 100ns).

 

Avrum

Tags (1)
3 Replies
Moderator
Moderator
2,050 Views
Registered: ‎05-31-2017

Re: Vivado - Post synthesis simulation

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Hi @aimatee,

 

Post-Synthesis timing simulation uses the estimated timing delay from the device models. So, you might me seeing multiple clock cycle delays for output.

 

Thanks & Regards,
A.Shameer

Historian
Historian
2,651 Views
Registered: ‎01-23-2009

Re: Vivado - Post synthesis simulation

Jump to solution

In post synthesis simulation, the primitive devices used as part of the simulation (the model of the flip-flop) also model the startup delay of the FPGA. When an FPGA finishes downloading its bitstream, it stays in a built in reset state due to the "global set reset (GSR)". This holds the FPGA in the configuration state for "some time". In post-sythesis simulation this time is modeled.

 

Most likely, the 0->1 transition you are seeing at time 105 is due to the deassertion of GSR.

 

Take a look at the waveforms later in time - they will probably behave as you expect. Alternatively, keep your reset asserted for a significantly longer period of time (greater than 100ns).

 

Avrum

Tags (1)
Highlighted
Visitor aimatee
Visitor
1,996 Views
Registered: ‎02-24-2018

Re: Vivado - Post synthesis simulation

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Thanks Avrum!

This indeed is the reason. I extended the reset and it worked.

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