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Visitor anas2012a95
Visitor
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Registered: ‎11-07-2018

Vivado: RAM Simulation with wrong output

Hi all, 

Urgent help is needed. 

I am using Block Memory Generator v8.4 in Vivado 2018.3 to generate a BRAM in stand alone mode. The problem I'm facing is that I can write properly to the RAM but I can only read part of the data correctly! The other part is simpely zeros! 
This is very strange as I am sure that the correct data is actually delivered to the internal pin of the RAM. So, the RAM definitely recieves the correct data but doesn't store them. 

These are the RAM options: 

Capture23423.PNGCapture34152.PNG

 

These are the simulation results: Capture123.PNGyou can see from the simulation that the correct data is delivered to the RAM, however, this is the testbench in case is needed: 

 

  clk200M:  process
  begin
    clk_200M <= '0';
    wait for clk200M_period/2;
    clk_200M <= '1';
    wait for clk200M_period/2;
  end process;
  
  clk16K:  process
  begin
    clk_16K <= '0';
    wait for clk16K_period/2;
    clk_16K <= '1';
    wait for clk16K_period/2;
  end process;
  
  stimulus: process
    variable x1: std_logic_vector(31 downto 0);
    variable x2: std_logic_vector(33 downto 0);
    variable current_line1 : line;
    variable current_line2 : line;
  begin
    reset <= '1';
    wait for 10 ns;
    reset <= '0';
    X_RAM_full <= '0';
    -----------------------------
    for i in 0 to 2047 loop     -- Writing to RAM
        ADC_output_valid <= '1';
        readline(Fout1,current_line1);
        read (current_line1,x1);
--        ADC_output_SLV <= to_slv(to_sfixed(x1,0,-33));
        ADC_output_SLV <= "00" & x1;
--        x1_test <= "00" & x1;
        if (i = 2047) then
            null;
        else
            wait for clk16K_period;
        end if;
    end loop;
    
wait for clk200m_period; wait for clk200m_period; wait on input_data_RAM_is_Full; for i in 0 to 2047 loop -- x2 := to_sfixed(data_out,0,-33); x2 := data_out; x2_test <= data_out; write(current_line2,x2); writeline(Fout2,current_line2); wait for clk200m_period; end loop; X_RAM_full <= '1'; wait; end process; end;

This is the source code if needed: 

 writing_process:
    process(reset,clk_16k,X_RAM_full) 
    begin 
        if (reset = '1') then
            counter <= (others => '0');
            full <= '0';
        elsif   (X_RAM_full = '1') then
            full <= '0';
        elsif   (full = '0') then
            if (clk_16k'event and clk_16k = '1') then     
--                data_out <= std_logic_vector(shift_right(signed(ADC_output_SLV),3)); -- normalizing the input signal by dididing values by 8 
                if (counter = "11111111111") then  -- counter = 2048, maximum address
                    full <= '1';
                    counter <= (others => '0');
                else
                    data_out <=ADC_output_SLV;
                    counter <= counter +1;
                end if;        
            end if;
        end if;
    end process;    

    Reading_process:
    process(reset,clk_200M,full)
    begin 
        if (reset = '1') then
            counter1 <= (others => '0');
            read <= (others => '0');
        elsif   (read <2) then
                read <= read+1;
        elsif   (full = '1' and read = 2) then    
            if (clk_200M'event and clk_200M = '1') then
                if (counter1 = "11111111111") then       -- counter1 = 2048, maximum address
                    counter1 <= (others => '0');
                else
                    counter1 <= counter1 +1;
                end if;
            end if;
        end if;
    end process;
    
    input_data_RAM_is_Full <= full;
    address <= counter when full ='0' else counter1;
    write <= "1" when full ='0' else "0";

I'm writing and reading at different speeds. 

The address is incrementing as expected. The data is received at the internel pin of the RAM correctly. Write signal is 1, and the clock is clocking! :\ 
Any help is really apprecicate it!! 

Many thanks !!

 

Anas

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