09-25-2015 02:55 AM
I'm very confused as to why Vivado Sim is showing me a conflict on the input to my shift register.
I want to delay a signal by X cycles, so I write:
signal delay_reg(X downto 0) := (others => '0');
delay_reg'high <= sig_in;
sig_out <= delay_reg(0);
delay_proc: process(clk) is
if rising_edge (clk) then
for i in 0 to (delay_reg'high - 1) loop
delay_reg(i) <= delay_reg(i+1);
But as soon as sig_in goes high I get a conflict and it thinks my process is trying to drive the highest bit in the shift register low, which I'm not.
Any thoughts? I have tried various permutations, including defining a variable in the process that is an integer of the value delay_'high -1, just to check the loop is operating in the correct range, and it is.
I have just tried changing the loop to work from 0 to delay'high -2. Now the conflict on bit delay_reg'high still exists, but the conflict does not ripple through the shift register. this makes no sense!
I'm using Vivado 2014.2 if that helps.
09-25-2015 03:10 AM
moving the two concurrent assignments into the clocked process (and reducing the delay value X by 2 to accomdate to two extra cycles...) fixes the problem.
I don't see why both shouldn't work though. In any case, there could still be a conflict, it's just that with them being in the same process the latter of the assignments would be made and the first one ignored, so it would still work.
09-25-2015 11:29 AM
I believe that it is not legal to assign some bits of a vector in one process and other bits in a different process, or continuous assignment. If you try to synthesize the original code, do you get "multisource" errors?
09-26-2015 02:07 AM
I don't know. I ended up synthesizing the second attempt (all in one clocked process).
I didn't know whether it was legal or not. It certainly should work.