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Visitor
Visitor
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Registered: ‎02-09-2019

Vivado Sim warning axi missing port aclk

Using Vivado 2018.3

Vivado behaviorial simulation produces warning in tcl window:  

WARNING: [Wavedata 42-559] Protocol instance "/tb_top_lvla/dut/system_i//fpdp_intfc_0/m1_axi_rx" was created but is non-functional for the following reason(s):
Required port "ACLK" is missing

Implementation is a user generated VHDL module bd connected to Aurora8B10B IP core AXI port.  

The signal "ACLK" does not exist in the Aurora 8B10B IP Core's AXI port, nor in the VHDL Module bd, so what does this warning mean and what should be done about it?  

The simulator runs, but the simulation results for the Aurora IP Core are indeed non-functional, no response, nothing happens.  

Possibly, the non-function of the core has some other cause, but best-start is to clean-up this ACLK warning issue.   

I need help and suggestions for what to do/try next. - Thx Carl S.  

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-27-2019

Hi @carlscott ,

The signal "ACLK" does not exist in the Aurora 8B10B IP Core's AXI port, nor in the VHDL Module bd, so what does this warning mean and what should be done about it?  

Actually AXI4 also need a clock to driver it , it not integrated in the AXI4 bus . For example :

Capture.PNG

S_axi_aclk is the clock to driver the AXI port. Maybe the clock is named other names, such as "m_axi_aclk" "s_axis_aclk" and so on.

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