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Voyager
Voyager
10,363 Views
Registered: ‎06-24-2013

Vivado Simulator 2014.1 segfaults.

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Attached is a small example which causes the Vivado Simulator to segfault.

 

ERROR: [XSIM 43-3316] Signal SIGSEGV received.
Printing stacktrace...

[0] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x511a6e]
[1] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x51f2c2]
[2] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x520956]
[3] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x53cf7e]
[4] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x53e736]
[5] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x53e8ae]
[6] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x53eccb]
[7] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x53e82e]
[8] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x53e8ae]
[9] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x54e905]
[10] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x54f22e]
[11] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5161fc]
[12] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5165bb]
[13] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x51041b]
[14] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5dbd13]
[15] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5d9495]
[16] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5dbc28]
[17] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5d9495]
[18] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x5bbd20]
[19] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x449794]
[20] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x452f58]
[21] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x44332e]
[22] /lib64/libc.so.6(__libc_start_main+0xed) [0x7f25923a832d]
[23] /opt/Xilinx/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x448b29]

Hope it helps,

Herbert

 

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Xilinx Employee
Xilinx Employee
15,792 Views
Registered: ‎04-16-2012

Hi Herbert,

 

Thanks for providing the missing file.

I am able to workaorund the issue. Attaching the working design for your reference.

 

It is a Vivado Simulator bug and need to be fixed. 

 

Thanks,

Vinay

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Xilinx Employee
Xilinx Employee
10,356 Views
Registered: ‎04-16-2012
Hi Herbert,

Thanks for the testcase. But the file "vivado_pkg.vhd" is missing in the attached zip file. Attach it to investigate the issue.

Thanks,
Vinay
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Voyager
Voyager
10,354 Views
Registered: ‎06-24-2013

Ah, sorry, it just defines the attributes.

 

You can grab it here: http://vserver.13thfloor.at/Stuff/XILINX/vivado_pkg.vhd

(for some reason the web interface does not allow to attach it, just says

 "The contents of the attachment doesn't match its file type.")

 

Best,

Herbert

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Moderator
Moderator
10,316 Views
Registered: ‎04-17-2011
From a quick analysis, the issue looks to be related to the function call:
ones_v := count_bits_f(din, '1');
zeros_v := count_bits_f(din, '0');

in count_bits.vhd. Something the tool is not liking.
But as this is a crash we would be filing a bug request.
Regards,
Debraj
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Xilinx Employee
Xilinx Employee
15,793 Views
Registered: ‎04-16-2012

Hi Herbert,

 

Thanks for providing the missing file.

I am able to workaorund the issue. Attaching the working design for your reference.

 

It is a Vivado Simulator bug and need to be fixed. 

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
10,306 Views
Registered: ‎02-14-2014

Hi Herbert,

 

As Debraj mentioned that it is an issue with the function, if you slightly modify your architecture RTL_COUNT as shown below, you will be able to resolve the issue. I have written for loops separately outside the function.

 

architecture RTL_COUNT of count_bits is

attribute KEEP_HIERARCHY of RTL_COUNT : architecture is "TRUE";
begin

out_proc : process (clk)
variable ones_v : natural range 0 to 8;
variable zeros_v : natural range 0 to 8;
begin
if rising_edge(clk) then
-- ones_v := count_bits_f(din, '1');
for I in din'range loop
if din(I) = '1' then
ones_v := ones_v + 1;
end if;
end loop;
--zeros_v := count_bits_f(din, '0');
for I in din'range loop
if din(I) = '0' then
zeros_v := zeros_v + 1;
end if;
end loop;

ones <= to_unsigned(ones_v, 4);
zeros <= to_unsigned(zeros_v, 4);
end if;
end process;

end RTL_COUNT;

 

Regards,
Ashish
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Voyager
Voyager
10,040 Views
Registered: ‎06-24-2013

Problem still exists in Vivado 2014.2.

 

Best,

Herbert

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Adventurer
Adventurer
9,543 Views
Registered: ‎03-03-2010

To add to this problem, I saw something simmilar (Vivado 2014.1):

 

ERROR: [XSIM 43-3316] Signal SIGSEGV received.
Printing stacktrace...

[0] /media/work/opt/Vivado/2014.1/lib/lnx64.o/libxsimverific.so(Verific::VeriTreeNode::StaticSizeSign(Verific::ValueTable*, Verific::VeriConstraint const*) const+0x1c) [0x7fde33807b8c]
[1] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x491cd2]
[2] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x4996b7]
[3] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x499deb]
[4] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x492269]
[5] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x49a296]
[6] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x499ef1]
[7] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x49142d]
[8] /media/work/opt/Vivado/2014.1/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x44) [0x7fde33929c84]
[9] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x49ad38]
[10] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x48b152]
[11] /media/work/opt/Vivado/2014.1/lib/lnx64.o/libxsimverific.so(Verific::VeriVisitor::TraverseArray(Verific::Array const*)+0x44) [0x7fde33929c84]
[12] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x49ad38]
[13] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x48a87d]
[14] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x459087]
[15] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x449654]
[16] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x452d11]
[17] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x44332e]
[18] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xfd) [0x7fde3236aead]
[19] /media/work/opt/Vivado/2014.1/bin/unwrapped/lnx64.o/xelab() [0x448b29]

 

I also had these two warnings:

 

WARNING: [VRFC 10-278] actual bit length 0 differs from formal bit length 12 for port addra 
WARNING: [VRFC 10-278] actual bit length 0 differs from formal bit length 12 for port addrb

 

It turns out that one of the struct elements had a bit length of [-1:0] due to an error in the definition. This the signal to which the "actual bit length of 0" is referring. 

 

This signal was connected to the block memory generator  IP core.

 

So if you see this segfault, check your warnings and make sure that your struct definitions are correct.

 

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Observer
Observer
6,861 Views
Registered: ‎05-26-2014

@debrajr

I face the exact same error with Vivado 2015.3.  "ERROR: [XSIM 43-3316] Signal SIGSEGV received."  Is there any progress or more information about that bug that would get me out of that? Is there any kind of operation, structure that should be avoided in the simulation code that would prevent stumbling on that bug?

 

Thanks 

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