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Visitor
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Registered: ‎11-14-2015

Vivado Simulator 2015.3, Simulation Step is stucked

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Hello,

 

Since I've being learning VHDL on Vivado at school, I installed it on my computer, but as now I'm unable to do any simulation.

 

When I launch a Behavioral simulation using a test bench file, the TCL console shows :

INFO: [USF-XSim-98] *** Running xsim
   with args "GBF_behav -key {Behavioral:sim_1:Functional:GBF} -tclbatch {GBF.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.3

and stay like this without doing anything.

 

The log :

 

Vivado Simulator 2015.3
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: D:/Softspace/Xilinx/Vivado/2015.3/bin/unwrapped/win64.o/xelab.exe -wto 5c503d70bdac4e2cb12896cbc843d8a1 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot GBF_behav xil_defaultlib.GBF -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.constants
Compiling architecture behavioral of entity xil_defaultlib.WaveRom [waverom_default]
Compiling architecture behavioral of entity xil_defaultlib.RomReader [romreader_default]
Compiling architecture behavioral of entity xil_defaultlib.gbf
Built simulation snapshot GBF_behav

When I try to stop the process, the TCL console shows :

INFO: [Common 17-41] Interrupt caught. Command should exit soon.

and Vivado stay on Canceling. Pleaser wait...

 

The degisn feature a common ROM with only 512 value in it, and a small module to read it.

 

The test bench file :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library WORK;
use WORK.CONSTANTS.ALL;


entity tb_GBF is
end tb_GBF;
 
architecture behavioral of tb_GBF is 

component GBF
    Port ( clk : in std_logic;
       rst : in std_logic;
       wave : out std_logic_vector (CNA_RANGE - 1 downto 0));
end component;
    
--Inputs
signal clk : std_logic;
signal rst : std_logic;

--Outputs
signal wave : std_logic_vector(CNA_RANGE - 1 downto 0);
 
constant clock_period : time := 10 ns;
 
begin
    -- Instantiate the Unit Under Test (UUT)
    uut: GBF
    port map (clk => clk, rst=>rst, wave => wave);

 -- Clock process definitions
   clock_process : process
   begin
		clk <= '0';
		wait for clock_period/2;
		clk <= '1';
		wait for clock_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
      rst<='0';	
      -- hold reset state for 100 ns.
      wait for 100 ns;	
      rst<='1';
      wait for clock_period*10;
      rst<='0';

      -- insert stimulus here 
   end process;

END;

 I'm using Windows 10, maybe it could be a reason Vivado Simulator remain stucked like that.

 

Any idea ?

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Moderator
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16,684 Views
Registered: ‎07-01-2015

Re: Vivado Simulator 2015.3, Simulation Step is stucked

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Hi @kinxil,

 

I tried at my end.

It's working at my end. I have attached the snapshot for your reference. So it seems OS specific issue.

 

Please close this thread by marking as "Accept as solution" if your query is addressed.

 

Thanks,
Arpan

Thanks,
Arpan
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Moderator
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Registered: ‎07-01-2015

Re: Vivado Simulator 2015.3, Simulation Step is stucked

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Hi @kinxil,

 

Windows 10 is not supported. For supported OS please refer page 14 of following link
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug973-vivado-release-notes-install-license.pdf

 

Can you try running an example design if it helps? Select may be Wavegen project from example design and see if it runs.

 

Thanks,
Arpan

Thanks,
Arpan
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Moderator
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Registered: ‎07-01-2015

Re: Vivado Simulator 2015.3, Simulation Step is stucked

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Hi @kinxil,

 

Have you tried with example design?

 

Can you please share the whole code so that I can check at my end and let you know if it's related to OS or code?

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
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Visitor
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Registered: ‎11-14-2015

Re: Vivado Simulator 2015.3, Simulation Step is stucked

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I guess it's OS related. I'm trying to run WaveGen and the same problem remains. I also encountered it with another project sample from the web which was supposed to generate waveforms using short code. I'll try to install ModelSim Student Edition and find out if W10 accepts it or not. If not... duh I guess it's time to come back to W8.1 or W7.

 

I linked the vhd files of the modules.

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Moderator
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16,685 Views
Registered: ‎07-01-2015

Re: Vivado Simulator 2015.3, Simulation Step is stucked

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Hi @kinxil,

 

I tried at my end.

It's working at my end. I have attached the snapshot for your reference. So it seems OS specific issue.

 

Please close this thread by marking as "Accept as solution" if your query is addressed.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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