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londonaurox
Newbie
Newbie
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Registered: ‎02-10-2019

Vivado Simulator Bit Length Restrictions

I'm wondering if there are any signal bit length restrictions in the Vivado simulator. I've come across bit length display restrictions, which I also have a question about, but nothing specifying the limitations of the simulator itself. For the display limitation in the simulator, I came across the following: https://www.xilinx.com/support/answers/59194.html Are there any alternative ways to display wide bit signals in the Vivado simulator that could make viewing more manageable? Any insight into this would be greatly appreciated. Thank you
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bandi
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Registered: ‎09-15-2016

Hi @londonaurox,

I hope you are trying to view signals with wide bits in Vivado simulator. Can you please try using the below commands and check if it helps.

To limit the number of digits to display for vectors, use the set_property array_display_limit <number> [current_sim] command, where it is the number of bits to display.

To set a display limit, use the Tcl command set_property DISPLAY_LIMIT <number> [current_wave_config].

Can you please refer the below forum post :

https://forums.xilinx.com/t5/Simulation-and-Verification/set-property-display-limit-not-allowing-for-large-objects-to-be/td-p/886669

For more information, please refer the below user guide page#55,78 :

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug900-vivado-logic-simulation.pdf 

 

Thanks & Regards,
Sravanthi B
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londonaurox
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Registered: ‎02-10-2019

Thank you kindly bandi.  This was the information I was looking for.

Have a good one!

 

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bandi
Moderator
Moderator
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Registered: ‎09-15-2016

Hi @londonaurox ,

Glad to know that the information provided was helpful. Can you please close this thread by marking the post which helped as accepted solution.

Thanks & Regards,
Sravanthi B
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