UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
202 Views
Registered: ‎10-31-2017

Vivado Simulator: error on post-synthesis simulation.

I am simulating a project based on Vivado's Base Zinq example project. Behavioral simulation is OK but I would like to run the post sinthesis funcional simulation.

I getting errors, listed below:

[VRFC 10-2991] 'fpga_soft_reset' is not declared under prefix 'inst' ["C:/Users/elder/Desktop/tmp/project_6/project_6.srcs/sim_1/imports/base_zynq/zynq_tb.v":84]
[VRFC 10-2991] 'write_data' is not declared under prefix 'inst' ["C:/Users/elder/Desktop/tmp/project_6/project_6.srcs/sim_1/imports/base_zynq/zynq_tb.v":91]
[VRFC 10-2991] 'read_data' is not declared under prefix 'inst' ["C:/Users/elder/Desktop/tmp/project_6/project_6.srcs/sim_1/imports/base_zynq/zynq_tb.v":92]

The lines of the Verilog testbench that cause the errors are:

tb.zynq_sys.base_zynq_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.write_data(32'h40000000,4, 32'hDEADBEEF, resp);
tb.zynq_sys.base_zynq_i.processing_system7_0.inst.read_data(32'h40000000,4,read_data,resp);

What is the cause of these errors? Is there a way to fix them?

0 Kudos
3 Replies
Scholar xilinxacct
Scholar
191 Views
Registered: ‎10-23-2018

Re: Odd error when trying to run Vivado Simulator [VRFC 10-149]

0 Kudos
Moderator
Moderator
95 Views
Registered: ‎05-31-2017

Re: Vivado Simulator: error on post-synthesis simulation.

Hi @eldercosta ,

As Behavioural Simulation is working fine and as you are facing issues only with the post-synthesis simulation, there might be chances of Synthesis trimming the signals. So, please check in the synthesis log if the signals are getting trimmed and modify your code such that the signals don't get trimmed or you can apply the dont_touch property on the signals/ports that are getting trimmed, then synthesize the design and try running post-synthesis simulation.

0 Kudos
Adventurer
Adventurer
54 Views
Registered: ‎10-31-2017

Re: Vivado Simulator: error on post-synthesis simulation.

Hello, @shameera 

 

Thank you for chiming in.

 

Notice the errors occur in an unmodified BaseZynq example project. I assumed it would run smoothly. Below a more thorough excerpt of the TCL log (previous steps ran fine):

 

INFO: [USF-XSim-69] 'compile' step finished in '6' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.sim/sim_1/synth/func/xsim'
Vivado Simulator 2018.3
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto 248d0ba981f54d95b84d382a43721c86 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L xilinx_vip -L unisims_ver -L secureip --snapshot tb_func_synth xil_defaultlib.tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-2991] 'fpga_soft_reset' is not declared under prefix 'inst' [C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.srcs/sim_1/imports/base_zynq/zynq_tb.v:84]
ERROR: [VRFC 10-2991] 'fpga_soft_reset' is not declared under prefix 'inst' [C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.srcs/sim_1/imports/base_zynq/zynq_tb.v:85]
ERROR: [VRFC 10-2991] 'write_data' is not declared under prefix 'inst' [C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.srcs/sim_1/imports/base_zynq/zynq_tb.v:88]
ERROR: [VRFC 10-2991] 'write_data' is not declared under prefix 'inst' [C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.srcs/sim_1/imports/base_zynq/zynq_tb.v:91]
ERROR: [VRFC 10-2991] 'read_data' is not declared under prefix 'inst' [C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.srcs/sim_1/imports/base_zynq/zynq_tb.v:92]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2181.188 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.sim/sim_1/synth/func/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/elder/Desktop/tmp/xxxyyy/xxxyyy.sim/sim_1/synth/func/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 2181.188 ; gain = 207.684
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

 

I do not know if this is related but years ago I had to tinker with Vivado's files (2016.2 at that time) to have post synthesis simulation running. I do not remember what I did and what files I changed though. At that time my coworkers created TCL scripts to create and configure projects that fixed the issues and post synthesis simulation runs fine with the projects managed this way.

However, the aforementioned simulations exercise only subsystems and do not use the utility functions (write_data, read_data etc.) that perform bus access like the Base Zynq project. Being able to using those functions will help me to check the integrated logic.

FWIW I usually run the post-synthesis functional to make sure the logic works as intended as I learned years ago sometimes there is a disagreement between behavioral and post-synthesis or post-implementation simulations caused by subtle coding mistakes.

FWIW I use VHDL, not Verilog like the example project does. However, I suspect the errors that occur during elaboration are not HD language related.

Again, thanks for your support.

Elder.

 

 

0 Kudos