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Newbie
Newbie
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Registered: ‎08-05-2020

Vivado UVM Simulation Error: pop_front is not declared under prefix...

Hi,

I am trying to run a UVM simulation in Vivado 2019.2 but I am having issues with a line that is generating an error. I went through all of the steps in the post about UVM support in Vivado (https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/UVM-Universal-Verification-Methodology-Support-in-Vivado/ba-p/1070861) so I am fairly confident that I have Vivado set up to run a UVM simulation. Also, the UVM simulation ran in VCS vM-2017.03-SP2 without any problems so as far as I know the UVM code functions correctly. I switched to Vivado because I added some Xilinx IPs (AXI Quad SPI and AXI Data Width Converter) to the project and I was running into a lot of issues trying to simulate in VCS after that. I did not modify the UVM code at all throughout this process.

The problem is inside of the sequence class. The two lines of interest to me are: 

----------------------------------------------------------------------------------------------------------------------------wait(p_sequencer.rsp_q.size());

$display(“Receive -> %02x”, p_sequencer.rsp_q.pop_front().rx_data_out);
----------------------------------------------------------------------------------------------------------------------------

When I try to run the simulation I get the following errors:

----------------------------------------------------------------------------------------------------------------------------ERROR: [VRFC 10-2991] 'pop_front' is not declared under prefix 'rsp_q' [../../../../AXICross_Dev_Vivado_uvm.srcs/sim_2/imports/uvm_1.2/../env/uart_sequence.sv:36]

ERROR: [VRFC 10-2991] 'pop_front' is not declared under prefix 'rsp_q' [../../../../AXICross_Dev_Vivado_uvm.srcs/sim_2/imports/uvm_1.2/../env/uart_sequence.sv:48]
----------------------------------------------------------------------------------------------------------------------------

rsp_q is defined in the sequencer: 

----------------------------------------------------------------------------------------------------------------------------uart_trans rsp_q[$];
----------------------------------------------------------------------------------------------------------------------------

The uart_trans class extends uvm_sequence_item (which I believe extends uvm_object). The pop_front() function is defined in the uvm_queue class that is in xlnx_uvm_package.sv in the Xilinx program files. The uvm_queue class also extends uvm_object. The main thing that confuses me is that the size() function is also in the uvm_queue class so I am not sure why the line using the pop_front() function generates an error but the line above it using the size() function does not.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-10-2020

Please upload the complete project here so that we can look into the issue.

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