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Visitor
Visitor
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Registered: ‎04-28-2020

Vivado Xilinx 2019.2 : ERROR: [XSIM 43-3238] Failed to link the design.

Hi all

I have a simple half adder code that i am trying to simulade in Vivado on a Windows 10 machine, but i keep getting this error

ERROR: [XSIM 43-3238] Failed to link the design.

Below is my elaborate.log file

Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.2/bin/unwrapped/win64.o/xelab.exe -wto 3eaf8a6bd56f49248f71b173c00cfbcd --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot half_adder_tb_behav xil_defaultlib.half_adder_tb xil_defaultlib.glbl -log elaborate.log -L uvm
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.half_adder
Compiling module xil_defaultlib.half_adder_tb
Compiling module xil_defaultlib.glbl
ERROR: [XSIM 43-3238] Failed to link the design.

I tried adding the -L uvm flags as other solutions suggested but it is not woking, if anyone can kindly assist. Thank you.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Vivado Xilinx 2019.2 : ERROR: [XSIM 43-3238] Failed to link the design.

Would you please provide a test case to reproduce the issue locally?

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