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Contributor
Contributor
337 Views
Registered: ‎06-20-2019

Vivado behavioral simulation problem

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Hello,

 

I am trying to test a dummy design by using UVM codes which are provided by Xilinx. I am not adding these files one by one but I am showing setup the directory(/tools/Vivado/2018.3/data/systemverilog). However, I am observing an interesting behavior of the tool. After clicking on run behavioral simulation, I can get waveform window. However, I am not able to run simulation, the run all button is grayed out and cannot be clicked. Thus, I cannot run simulation. I tried to give tcl command but at that time, simulation continues till infinity and still I am seeing black waveform window which you can see below.

 

Selection_100.png

 

 

I would think that Vivado's systemverilog support is somehow restricted but I commented out the uvm related stuff from my testbench top.The code is like

module top;

  `include "uvm_macros.svh"
  // import uvm_pkg::*;
  // import my_testbench_pkg::*;

  wire reset;
  reg clock;
  wire cmd;
  wire[7:0] data;
  wire[7:0] addr;

   dut_if dut_if1();

   assign dut_if1.m_reset = reset;
   assign dut_if1.m_clock = clock;
   assign dut_if1.m_cmd = cmd;
   assign dut_if1.m_data = data;
   assign dut_if1.m_addr = addr;

dut dut1(.reset(reset), .clock(clock), .addr(addr), .data(data), .cmd(cmd)); // Clock generator initial begin clock = 0; forever #5 clock = ~clock; end initial begin #100ns; // Place the interface into the UVM configuration database // uvm_config_db#(virtual dut_if)::set(null, "*", "dut_vif", dut_if1); // Start the test #100ns; // run_test("my_test"); end endmodule

When I click on something from Scope window I see a window that shows "Unknown exception occured" error which I cannot give any meaning. Also, tcl console shows me the following:

xsim.dir/top_behav/xsimk: symbol lookup error: xsim.dir/top_behav/xsimk: undefined symbol: uvm_dpi_get_next_arg_c
Command failed: Simulator command interrupted.

Simulation engine not responding

 

I haven't added any uvm_dpi... btw. There are some files under simulation sources tough which are related to uvm_pkg.

 

 

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Scholar richardhead
Scholar
170 Views
Registered: ‎08-01-2012

Re: Vivado behavioral simulation problem

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Vivado only supports certain SV features. UVM uses most of the features of SV so until Vivado gets full SV support it wont be able to support UVM.

This is also why UVM support comes at extra cost for some simulators.

3 Replies
Moderator
Moderator
213 Views
Registered: ‎09-15-2016

Re: Vivado behavioral simulation problem

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Hi @yhy.xilinx ,

UVM is not supported in Vivado 2018.3. Hence, can you please try removing all the sources of UVM and its references then try resetting and rerunning simulation. If you are still facing issues then can you please share a complete test case to check this issue at our end.

Also, can you please try running simulation in our latest version of Vivado 2019.1 and check if you are still facing the same issue.

Thanks & Regards,
Sravanthi B
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Contributor
Contributor
195 Views
Registered: ‎06-20-2019

Re: Vivado behavioral simulation problem

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There were some comments on other discussions about insufficient support of VIVADO but I thought that it might be exceeded since it supports systemverilog in 2018.3. If it can support systemverilog, why cannot it support UVM? What is insufficient is hard to get because we can already write systemverilog testbenches. UVM just consists of SystemVerilog macros. My main purpose was already using UVM features on VIVADO. If i see any difference with 2019.1, I will let you know. Thank you.
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Highlighted
Scholar richardhead
Scholar
171 Views
Registered: ‎08-01-2012

Re: Vivado behavioral simulation problem

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Vivado only supports certain SV features. UVM uses most of the features of SV so until Vivado gets full SV support it wont be able to support UVM.

This is also why UVM support comes at extra cost for some simulators.