Vivado crashes with VHDL 2008 and generic type BRAM

[paclopes]

In my project, I was using the following BRAM component:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity BRAM is
generic (size: integer; type data_type);
Port ( addr: in unsigned(length(size-1)-1 downto 0);
data_in : in data_type;
data_out : out data_type;
write : in std_logic;
read : in std_logic;
clock : in std_logic);
end BRAM;

architecture Behavioral of BRAM is
type ram_type is array (0 to size-1) of data_type;
signal ram: ram_type;
begin
process(clock)
begin
if rising_edge(clock) then
if read = '1' then
data_out <= ram(to_integer(addr));
end if;
if write='1' then
ram(to_integer(addr)) <= data_in;
end if;
end if;
end process;
end Behavioral;

wich uses a generic data_type of VHDL 2008. However, when I run a simulation the simulator throws an exeption and exists. This is the output of the TCLConsole:

launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Documents/Profissional/ID/Codes/DPC_FPGA/work_VHDL/dpcVx1/dpcVx1.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'DP_coder_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Documents/Profissional/ID/Codes/DPC_FPGA/work_VHDL/dpcVx1/dpcVx1.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj DP_coder_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "D:/Documents/Profissional/ID/Codes/DPC_FPGA/work_VHDL/dpcVx1/dpcVx1.srcs/sources_1/imports/dpc2/DP_coder_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'DP_coder_tb'
WARNING: [VRFC 10-2115] shared variables must be of a protected type [D:/Documents/Profissional/ID/Codes/DPC_FPGA/work_VHDL/dpcVx1/dpcVx1.srcs/sources_1/imports/dpc2/DP_coder_tb.vhd:24]
WARNING: [VRFC 10-2115] shared variables must be of a protected type [D:/Documents/Profissional/ID/Codes/DPC_FPGA/work_VHDL/dpcVx1/dpcVx1.srcs/sources_1/imports/dpc2/DP_coder_tb.vhd:25]
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Documents/Profissional/ID/Codes/DPC_FPGA/work_VHDL/dpcVx1/dpcVx1.sim/sim_1/behav/xsim'
"xelab -wto 89b0112bfddc4032909d062e769de869 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot DP_coder_tb_behav xil_defaultlib.DP_coder_tb -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 89b0112bfddc4032909d062e769de869 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot DP_coder_tb_behav xil_defaultlib.DP_coder_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Printing stacktrace...

[0] (KiUserExceptionDispatcher+0x2e) [0x7ff80f84e70e]
[1] (ISIMC::Options::parseVlogcompCommandLine+0xf12b7) [0x7ff7f74dc267]
[2] (ISIMC::VhdlCompiler::saveParserDump+0x947df) [0x7ff7f73d0d7f]
[3] [0x7ff7f70f6794]
[4] [0x7ff7f70fa5f2]
[5] [0x7ff7f70f8e86]
[6] (ISIMC::Options::parseVlogcompCommandLine+0xae3d79) [0x7ff7f7eced29]
[7] (BaseThreadInitThunk+0x14) [0x7ff80e114034]

Done

However, when I remove the generic type and use several files with different types (common VHDL files) the project works without a problem. I am also able to do synthesis of the VHDL 2008 project with no errors.

I'm using:

Vivado v2019.1 (64-bit) SW Build: 2552052 on Fri May 24 14:49:42 MDT 2019 IP Build: 2548770 on Fri May 24 18:01:18 MDT 2019

[xilinxacct · Accepted solution]

@paclopes 

Not 100% sure that this is your issue, but are you aware the VHDL 2008 is not fully supported. It is only partially supported. Not sure what is in and what is out. It is just classified as a 'synthesizable subset'.

Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)

[richardhead]

@paclopes 

Currently the Xilinx Simulator is lagging far behind the synth engine for 2008 support.

2019.1 appears to be able to properly synthesise generic types AND generic functions on entities, something that ActiveHDL doesnt currently support.

Forget about 2008 in the simulator though. The simulator has been out of step for over a year.

NOTE: for a more useful and capable simulator - you can get modelsim from Intel in their webpack for free...

[luzhandr]

That's odd,  generic types are supposed to be supported (UG 900, Table C-1).

Also, you can try to synthesise the design and run post-synthesis functional simulation.  A good chance, that it will work that way

[drjohnsmith]

And its VHDL,

so if its a tool problem, little likelyhood of Xilinx even noticing let alone fixing

Now if you were in SystemVerilog, or even better HLS, they would be all over you.

[maps-mpls]

---

@drjohnsmith wrote:

And its VHDL,

so if its a tool problem, little likelyhood of Xilinx even noticing let alone fixing

Now if you were in SystemVerilog, or even better HLS, they would be all over you.

---

I like your optimism.

[paclopes]

Ok, I rewrote the thing without VHDL 2008, not a hard-task any way... Thanks