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Visitor nmoezzi
Visitor
7,161 Views
Registered: ‎08-17-2016

Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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Hi,

 

At some point in my RTL simulation, I observed that the Vivado simulator doesn't behave correctly for a D flopflop I have description below. I have also attached the waveform. The issue is that at posedge of the pclk, pwdata should be sampled into psdata_int. But this doesn't happen and pwdata_int stays 0. 

 

always_ff @(posedge pclk, posedge ares)
if (ares)
    pwdata_int <= 8'd0;
else if (pwrite)
    pwdata_int <= pwdata;
else
    pwdata_int <= 8'b0;

 

 

The behavior is correct when I use VCS simulator for the same code. Is there a solution for thsi type of behavior in Vivado?

 

I am using Vivado v2016.2 (64-bit).

 

Thanks,

Nariman

 

 

 

Vivado_and_VCS_Simulation.png
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1 Solution

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Teacher muzaffer
Teacher
13,274 Views
Registered: ‎03-31-2012

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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this maybe a race condition (or a hold violation). Is pwrite being generated by a flop registered with pclk? If not, try it that way.

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9 Replies
Xilinx Employee
Xilinx Employee
7,154 Views
Registered: ‎08-01-2008

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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-- try this code

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity D_FF is
PORT( D,CLOCK: in std_logic;
Q: out std_logic);
end D_FF;

architecture behavioral of D_FF is
begin
process(CLOCK)
begin
if(CLOCK='1' and CLOCK'EVENT) then
Q <= D;
end if;
end process;
end behavioral;
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Teacher muzaffer
Teacher
13,275 Views
Registered: ‎03-31-2012

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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this maybe a race condition (or a hold violation). Is pwrite being generated by a flop registered with pclk? If not, try it that way.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

Voyager
Voyager
7,133 Views
Registered: ‎04-21-2014

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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See user guide 901 (which covers synthesis, not simulation).  sub-section titled "sequential always block"

 

always_ff @(posedge pclk, posedge ares)
if (ares)

  // asynchronous part
  pwdata_int <= 8'd0;
else

  begin

    // synchronous part

     if (pwrite)
      pwdata_int <= pwdata;
     else
      pwdata_int <= 8'b0;

  end

 

 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Xilinx Employee
Xilinx Employee
7,116 Views
Registered: ‎07-31-2012

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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Can you try a quick test by extending the pwrite high for more time so that it extends further than the rising edge of pclk. Just want to ensure the pwrite high is not being latched at the rising edge of the pclk rising edge due to a glbl.v file which adds inherent delay to the simulation.
Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
7,111 Views
Registered: ‎10-24-2013

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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Hi @nmoezzi

Can you please attach the sample testcase here?

Thanks,Vijay
--------------------------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
7,104 Views
Registered: ‎08-01-2008

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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// Check this verilog code 

/-----------------------------------------------------
// Design Name : dff_sync_reset // File Name : dff_sync_reset.v // Function : D flip-flop sync reset // Coder : Deepak Kumar Tala //----------------------------------------------------- module dff_sync_reset ( data , // Data Input clk , // Clock Input reset , // Reset input q // Q output ); //-----------Input Ports--------------- input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- reg q; //-------------Code Starts Here--------- always @ ( posedge clk) if (~reset) begin q <= 1'b0; end else begin q <= data; end endmodule //End Of Module dff_sync_reset
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Visitor nmoezzi
Visitor
7,072 Views
Registered: ‎08-17-2016

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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The issue is gone after considering your suggestion with RTL modification in other parts of the design. Although I am still wondering if as @athandr

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Visitor nmoezzi
Visitor
7,069 Views
Registered: ‎08-17-2016

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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Forgot to mention the post from @muzaffer resolved the issue.

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Explorer
Explorer
7,021 Views
Registered: ‎09-07-2011

Re: Vivado doesn't simulate D-flipflop behavior in RTL correctly (VCS simullation looks good)

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The nasty thing is that an HDL  race condition can behave differently in different simulators.  I've discovered race condition differences with different versions of the same simulator, or even within the same version with different settings.