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Adventurer
Adventurer
1,199 Views
Registered: ‎01-15-2013

Vivado example design simulation error

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Hi,

 

I recently updated from Vivado 2018.2 to Vivado 2018.2.2 in Windows 10. The example base design used is a Base Zynq design (with a AXI GPIO and AXI BRAM). Before the version update, this example design worked using XSim. After the update, a new project was created and the example design fails simulation with the following error : 

 

INFO: [VRFC 10-163] Analyzing VHDL file "PROJECT_PATH/project_6/project_6.ip_user_files/bd/base_zynq/ip/base_zynq_axi_gpio_0_0/sim/base_zynq_axi_gpio_0_0.vhd" into library xil_defaultlib
ERROR: [VRFC 10-149] 'axi_gpio' is not compiled in library axi_gpio_v2_0_19 [PROJECT_PATH/project_6/project_6.ip_user_files/bd/base_zynq/ip/base_zynq_axi_gpio_0_0/sim/base_zynq_axi_gpio_0_0.vhd:57]
INFO: [VRFC 10-307] analyzing entity base_zynq_axi_gpio_0_0
ERROR: [VRFC 10-1504] unit base_zynq_axi_gpio_0_0 ignored due to previous errors [PROJECT_PATH/project_6/project_6.ip_user_files/bd/base_zynq/ip/base_zynq_axi_gpio_0_0/sim/base_zynq_axi_gpio_0_0.vhd:59]
INFO: [VRFC 10-240] VHDL file PROJECT_PATH/project_6/project_6.ip_user_files/bd/base_zynq/ip/base_zynq_axi_gpio_0_0/sim/base_zynq_axi_gpio_0_0.vhd ignored due to errors

where PROJECT_PATH is path of my project locally. Synthesis of the project seem to complete fine. It looks like AXI_GPIO simulation libraries need to be re-compiled. I believe this has to be done automatically for Xsim and manually for 3rd party simulation tools after a version update. Could anyone explain why and suggest solutions for the problem ? 

 

Paul 

 

 

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Adventurer
Adventurer
977 Views
Registered: ‎01-15-2013

回复: Vivado example design simulation error

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I don't think the problem will be solved until a new Vivado version is released or at least a patch. However, I managed to work around the problem. I cannot remember all the details but here is what I did :

In Settings of Vivado GUI, you can find IP project setting. Disable the option " Use Precompiled IP simulation libraries ". I think this change is sufficient but if it doesn't work, go to Simulation in IP project setting. Go to Advanced and disable incremental compilation.

Hope that works for you.

 

 

6 Replies
Xilinx Employee
Xilinx Employee
1,166 Views
Registered: ‎07-16-2008

回复: Vivado example design simulation error

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Did you upgrade the IPs and re-generate the output product?

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Adventurer
Adventurer
1,160 Views
Registered: ‎01-15-2013

回复: Vivado example design simulation error

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Hi,

 

Thanks for getting back on this question.

 

I didn't regenerate the IP because there was no report for outdated IP's in the project. I believe this was due to a minor update from version 2018.2 to 2018.2.2. Also, note that synthesis worked fine without errors. Is there a way to force an update for simulation libraries? 

 

I also created a new project with example template from Xilinx (Base Zynq design with AXI GPIO and AXI BRAM) and still encountered the same problem. 

 

 

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Xilinx Employee
Xilinx Employee
1,154 Views
Registered: ‎07-16-2008

回复: Vivado example design simulation error

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I can reproduce the failure with the Base Zynq example design. I agree something is broken in the pre-compiled Xsim libs.

I'll file a CR so that dev team can investigate and fix it.

Thank you for reporting this issue.

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Visitor blamberg_
Visitor
984 Views
Registered: ‎11-05-2018

回复: Vivado example design simulation error

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Hello,

is the problem solved now? I need the axi_gpio in 2018.2.2 and have the same problem.

 

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Adventurer
Adventurer
978 Views
Registered: ‎01-15-2013

回复: Vivado example design simulation error

Jump to solution

I don't think the problem will be solved until a new Vivado version is released or at least a patch. However, I managed to work around the problem. I cannot remember all the details but here is what I did :

In Settings of Vivado GUI, you can find IP project setting. Disable the option " Use Precompiled IP simulation libraries ". I think this change is sufficient but if it doesn't work, go to Simulation in IP project setting. Go to Advanced and disable incremental compilation.

Hope that works for you.

 

 

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Visitor blamberg_
Visitor
951 Views
Registered: ‎11-05-2018

回复: Vivado example design simulation error

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Thank you. I disabled both options and vivado works fine.

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