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391 Views
Registered: ‎11-08-2018

Vivado, export_simulation and modelsim 10.5c

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Hello,

First of all the context:
  - I am using Vivado 2018.3 + Modelsim 10.5c
  - I am targeting a Kintex KU115
  - I am trying to simulate the gtwizard ultrascale example design

  That being said, I used the export simulation function which iis given here below:

export_simulation  -lib_map_path "/path_to/CompileSimLib" -absolute_path -force -directory "/path_to/vivado/trial/gtwizard_ultrascale_0_ex/simuFolder" -simulator modelsim  -ip_user_files_dir /path_to/vivado/trial/gtwizard_ultrascale_0_ex/gtwizard_ultrascale_0_ex.ip_user_files" -ipstatic_source_dir /path_to/vivado/trial/gtwizard_ultrascale_0_ex/gtwizard_ultrascale_0_ex.ip_user_files/ipstatic" -use_ip_compiled_libs

When I try to launch the simulation from my Linux terminal (.sh file) I get the following error:

# 10.5c

# vsim -c -do "do" {simulate.do} -l simulate.log
# Start time: 15:04:52 on Apr 01,2019
# ** Error (suppressible): (vsim-19) Failed to access library 'work' at "work".
# No such file or directory. (errno = ENOENT)
# Error loading design
Error loading design
# End time: 15:04:52 on Apr 01,2019, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

 


But when I launch "do simulate.do" from Modelsim everything works fine.

So where am I missing to point to the work library?

Thank you for your help.

Regards,

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302 Views
Registered: ‎11-08-2018

回复: Vivado, export_simulation and modelsim 10.5c

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I've just found the problem! Actually there are 2 bugs in the generated compile.do and .sh files from Vivado:

1- In compile.do , the "work" mapping is missing --> Add vmap work modelsim_lib/work

2- In the .sh file: in the simulate function, the command vsim -64 -c -do "do {simulate.do}" -l simulate.log is erroneous, replace it by vsim -64 -do simulate.do -l simulate.log and everything will be fine.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Vivado, export_simulation and modelsim 10.5c

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I'd expect running the .sh script will source compile.do, elaborate.do and simulate.do sequentially.

Generally in compile.do, vlib command is specified to create work directory in the current directory. You may want to cross check the log files and target directories.

BTW, the compatible modelsim version with Vivado 2018.3 is 10.6c.

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Registered: ‎11-08-2018

回复: Vivado, export_simulation and modelsim 10.5c

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Hello Graces and thank you for your quick reply.

First of all regarding the version, yes I am working on getting the latest version (10.6e).

 

Any way, I added vlib work and now I get the foolowing error:

# vsim -c -do "do" {simulate.do} -l simulate.log
# Start time: 10:24:37 on Apr 02,2019
# ** Note: (vsim-3812) Design is being optimized...
# ** Error (suppressible): (vopt-19) Failed to access library 'work.{simulate' at "work.{simulate".
# No such file or directory. (errno = ENOENT)
# ** Error (suppressible): (vopt-19) Failed to access library 'work.{simulate' at "work.{simulate".
# No such file or directory. (errno = ENOENT)
# Error loading design
Error loading design
# End time: 10:24:37 on Apr 02,2019, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0

 

Please find here attached the files I generated from Vivado 2018.3 (export simu feature).

regards,

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Vivado, export_simulation and modelsim 10.5c

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Did you edit the compile.do and simulate.do? Why is there a duplicate creation of library work?

vlib modelsim_lib/work
vlib modelsim_lib/msim

vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/work

vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap work modelsim_lib/msim/work

What are the original generated scripts like?

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Registered: ‎11-08-2018

回复: Vivado, export_simulation and modelsim 10.5c

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These ARE the original scripts Graces obtained as I said by export_simulation by Vivadoo.

Is there a bug I am not aware of?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Vivado, export_simulation and modelsim 10.5c

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I gave it a try at my end (2018.3 + Modelsim 10.6c) but didn't observe the same vlib commands in compile.do & simulate.do.

Attached the scripts for your reference.

 

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Registered: ‎11-08-2018

回复: Vivado, export_simulation and modelsim 10.5c

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Hello Graces,

 

Same here, I just got the modelsim 10.7c. I gave it a try and I have the same commands as you....But unfortunately, the generated .sh file is still not working: I still have te same error message.

 

Did that work for you? the .sh file?

 

Rgds,

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Registered: ‎11-08-2018

回复: Vivado, export_simulation and modelsim 10.5c

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I've just found the problem! Actually there are 2 bugs in the generated compile.do and .sh files from Vivado:

1- In compile.do , the "work" mapping is missing --> Add vmap work modelsim_lib/work

2- In the .sh file: in the simulate function, the command vsim -64 -c -do "do {simulate.do}" -l simulate.log is erroneous, replace it by vsim -64 -do simulate.do -l simulate.log and everything will be fine.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Vivado, export_simulation and modelsim 10.5c

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I can source the .sh successfully "as is". There's no need to map the work library as the logical 'work' library is not loaded in vsim command, instead, 'xil_defultlib' is referenced.

Attached are the log files.

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Registered: ‎11-08-2018

回复: Vivado, export_simulation and modelsim 10.5c

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Still not working for me. So i think i am gonna stick to my solution. Thank you anyway.

 

Rgds

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