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8,769 Views
Registered: ‎08-25-2015

Vivado hangs at simulation

I was hoping to get a Xilinx person to comment on/give me recommendation for solving a problem that developed while simulating a vhdl design.

 

I have viv 2014.4, ubuntu 14.4.  I loaded up some vhdl source files that I need to examine in a gui project.  I created a testbench to do a sim of the design.  I started by creating the clocks and resets, this worked fine, the sim went off without a hitch.  I then added vhdl code to the tb to read the contents of a data file.  I had a few syntax errors in the file read code, but got through them.  When I tried to run the sim on these changes, the simulator started to hang.  I backed out the changes completely and now the simulator will not run for this project.

 

What is happening is xsimk gets spawned off and just sits there using 100% of its CPU.  The last thing on the tcl console is "run 1000ns".  If I background the thing it never comes back.  If I cancel it never finishes.  If I kill the xsimk, the gui comes back but anything I clock I get a MessageBox saying an internal error has occurred.  I have to quit vivado to get rid of this.

 

So I musta hosed the project files.  I deleted all the project files and started a new project from scratch.  The same thing happens.  This leads me to believe that vivado does not like something in the testbench, but I have no idea how to find what that is.  The tb is back to the version that I used to simulate the clocks and resets (which worked)

 

The odd thing is that another project simulates fine using the exact same vivado executable!

 

So what would cause vivado to start a sim and seemingly not finish it like I described?

 

Thanks

CFG

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Re: Vivado hangs at simulation

Hi @crazy_fpga_guy

 

Can you please post the simulation log file here? Also try using the latest version (2015.2) if you have access to.

Thanks,Vijay
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8,748 Views
Registered: ‎08-25-2015

Re: Vivado hangs at simulation

VJ,

    Theres three problems with this.  The sim log file is empty, I am working on a non-internet connected system, and I dont have the ability to upgrade the system I'm on.  I can transcribe and paraphrase small things if necessary but I cant get whole files over to the internet.

 

  I have to attempt to debug this the hard way, luckily I am working on linux.  What I am looking for is what happens under the hood when a sim is launched.  This way I can dig into the process and maybe monitor its steps and see what is going on.  Who spawns off xsimk?  What is xsimk doing and what is it looking for so it can exit properly?  This is the stuff that is missing in all the docs....

 

Thanks

CFG

 

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Moderator
Moderator
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Registered: ‎04-17-2011

Re: Vivado hangs at simulation

Do we have an equivalent of Windows Dependency Walker in Linux? If yes, then you can check it. xsimk is usually spawned by isim.exe.
http://www.dependencywalker.com/
Regards,
Debraj
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8,605 Views
Registered: ‎08-25-2015

Re: Vivado hangs at simulation

I want to get back to you all about what I discovered over the past few weeks of using Vivado.  First, I am using 2014.4 because that is the version that the targets vendor is supporting.  I have access to 2015.2 and I plan to test it against the problems I have been having and get back to you.

 

The thing I was having trouble with was actually a VHDL coding issue!  I was doing file I/O in a testbench and there was a problem with the code.  The bigger issue here is that tools dont work like typical "compilers".  Vivado dutifully launches an executable and the executable never comes back.  It doesnt like something in the code and it just goes into lala land.  The only resolution is to kill all the processes and relaunch from scratch.  The logs for the run are empty, you never get an idea of what exactly the problem is.  The tools can pick out a syntax error OK.  Missing delimiters, ranges on busses, semicolons, they all get picked up.  If there is an issue with the interpretation of the VHDL, good luck.  My approach to finding the reason for the hang was to revert back to VHDL 87 text I/O, then try binary I/O, then go back to VHDL 93 text I/O and then I stumbled on the problem.  This same situation occurs over and over again (with VHDL projects) where there is a hang and no indication of what the util does not like.

 

Its not like I have another option here.  Going the script route just eliminates the GUI.  I still have to use the same executables that go away and have to be killed.  It confounds me that a multi-thousand $ package is written like this.  If you hit cancel in the GUI, the GUI sez signal caught, please wait.  Apparently not, I have never got the synth tool to come back after a cancel.  These executables are spawned and there is no status from them.  The only way I know the synth is running on the big projects is to watch the process alloc mem!

 

So here is what I have to say:  Xilinx needs to put a debugging console interface into thier executables.  Something we can clip out and paste into the support site so you guys can tell us what is going on. 

 

A new question:  Where do I post questions about general vivado gui usage?

 

 

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Moderator
Moderator
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Registered: ‎04-17-2011

Re: Vivado hangs at simulation

You can post them in the Design Entry board:
https://forums.xilinx.com/t5/Design-Entry/bd-p/DEENBD
Regards,
Debraj
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