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Contributor
Contributor
774 Views
Registered: ‎11-10-2011

Vivado path issues

Using a VHDL package with global project options and scripts to simulation and implementation I find the following path issues.

Environment :
Ubuntu 16.04 LTS | ~$ echo $HOME => /home/daniel
Vivado 2017.4

First try: shorthand.
CONSTANT prog : STRING := "~/blackbox/Po/Files/IntDemo.mem";

Results:

Simu script
ERROR: [VRFC 10-2551] failed to open VHDL file '~/blackbox/Po/Files/IntDemo.mem' in mode 'r' [/media/Trabajo/ProyectosPersonales/P20180037/FPGA/Srcs/MCU/LRAM.vhd:36]

Build script
Build.tcl finalizado en 217 seg

Second try: environment variable  
CONSTANT prog : STRING := "$HOME/blackbox/Po/Files/IntDemo.mem";

Result:

Simu script
ERROR: [VRFC 10-2551] failed to open VHDL file '$HOME/blackbox/Po/Files/IntDemo.mem' in mode 'r' [/media/Trabajo/ProyectosPersonales/P20180037/FPGA/Srcs/MCU/LRAM.vhd:36]

Build script
ERROR: [Synth 8-3302] unable to open file '$HOME/blackbox/Po/Files/IntDemo.mem' in 'r' mode [/media/Trabajo/ProyectosPersonales/P20180037/FPGA/Srcs/MCU/LRAM.vhd:36]

Third try: full path

CONSTANT prog : STRING := "/home/daniel/blackbox/Po/Files/IntDemo.mem";

Results:

Simu script
Simulation GUI running

Build script
Build.tcl finalizado en 217 seg

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2 Replies
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Moderator
Moderator
741 Views
Registered: ‎07-16-2008

There's already a CR on this topic. Currently a path with environment variable is not recognized in Xsim.

 

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Contributor
Contributor
725 Views
Registered: ‎11-10-2011

Correction:

 

A path with environment variable is not recognized in Xsim or in implementation tool flow.

A path with shorthand is not recognized in Xsim.

 

So, I can conclude that Xilinx is using two different parsers; one for the implementation flow, another for the simulation flow. and there are problems in both flows.

 

 

 

 

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