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hmy1223
Newbie
Newbie
750 Views
Registered: ‎05-05-2019

Vivado simulation ERROR

我有一个.v文件已经被合成和移植,但是我不能用Modelism10.5c进行仿真。

what surprises me most is I can separately do simulation on every single IP core and other normal verilog file  with modelism10.5c.

The only change is I add a new .coe file instead in one FIR_comliper_v7.2

Details here:

** Error: (vsim-3060) <protected>(<protected>): Port '<protected>' not found in VHDL entity (<protected> connection).
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd
# ** Error: (vsim-3060) <protected>(<protected>): Port '<protected>' not found in VHDL entity (<protected> connection).
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd
# ** Error: (vsim-3060) <protected>(<protected>): Port '<protected>' not found in VHDL entity (<protected> connection).
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd
# ** Error: (vsim-3060) <protected>(<protected>): Port '<protected>' not found in VHDL entity (<protected> connection).
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd
# ** Error: (vsim-3060) <protected>(<protected>): Port '<protected>' not found in VHDL entity (<protected> connection).
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd
# ** Error: (vsim-3060) <protected>(<protected>): Port '<protected>' not found in VHDL entity (<protected> connection).
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd
# ** Fatal: (vsim-7) Failed to open <protected> file "<protected>" in <protected> mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Protected: /Tb_DownsampleFilter/uut/<protected> File: C:/Xilinx/Vivado/2017.4/data/ip/xilinx/fir_compiler_v7_2/hdl/fir_compiler_v7_2_vh_rfs.vhd Line: UNKNOWN
# FATAL ERROR while loading design

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2 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
746 Views
Registered: ‎05-22-2018

Hi @hmy1223 ,

 

Which Vivado version you are working with?

Thanks,

Raj

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shameera
Moderator
Moderator
701 Views
Registered: ‎05-31-2017

Hi @hmy1223 ,

From the shared error information, it seems that you are using Vivado 2017.4 and modelsim 10.5c.

For Vivado 2017.4 Modelsim 10.6b is the minimum compatible version. As you are using Modelsim 10.5c along with Vivado 2018.3 you might be facing this issue. Please check page 11 of UG 973 regarding the same.

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