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Visitor
Visitor
5,493 Views
Registered: ‎07-28-2016

Vivado simulation error 2016.2 - Failure: ERROR:add_1 must be in range [-1,DEPTH-1]

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Hello,

 

I tried to do a behavioural simulation for a design, but it stops far too early. The signal/variable add_1 mentioned in the Tcl console (see below) seems to be an internal one from an IP core or something.

Maybe there's an issue with the IP cores I am using? (which are: Floatingpoint 7.1, Fast Fourier Transform 9.0, FIFO Generator 13.1, Clocking Wizard 5.3)

Especially the fft-core is mentioned here with a similar error: http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-November/016684.html

 

How can I solve the problem or get around it? Any ideas? I appreciate any help.

 

Chris

 

 

 

The Tcl console shows these messages:

 

INFO: [Simtcl 6-17] Simulation restarted
run 200 us
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Note:
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note:
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Note:
******************************************************
  renorm_and_round_logic.vhd :
    FULL_MANT_RND1_DEL is using fast_input
    which will be faster, but create more FFs.
******************************************************
Time: 0 ps  Iteration: 0
Failure: ERROR:add_1 must be in range [-1,DEPTH-1]
Time: 290 ns  Iteration: 5
$finish called at time : 290 ns : File "C:/Vivado Projekte/v0.4Sender/0.4Sender.srcs/sources_1/new/frame_done.vhd" Line 39

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Visitor
Visitor
9,618 Views
Registered: ‎07-28-2016

Ok, I've found the reason:

The fft-ip core got an undefined clock enable at that time, which caused the simulation to stop.

 

So if you get this error drag all signals into the simulation and look for undefined ones.

Thanks for reading.

 

View solution in original post

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Visitor
Visitor
9,619 Views
Registered: ‎07-28-2016

Ok, I've found the reason:

The fft-ip core got an undefined clock enable at that time, which caused the simulation to stop.

 

So if you get this error drag all signals into the simulation and look for undefined ones.

Thanks for reading.

 

View solution in original post

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Xilinx Employee
Xilinx Employee
5,449 Views
Registered: ‎10-24-2013

Hi @crybe86

Please check if the below links helps.

https://forums.xilinx.com/t5/Simulation-and-Verification/vivado-2015-1-simulation-error-Failure-ERROR-add-1-must-be-in/td-p/600653

Thanks,Vijay
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