06-04-2019 09:51 AM
I am running a test with a system verilog file on Vivado 2017.4 and I can't get fread to work without a catastrophic failure of the simulator. Here is the code that fails:
reg [7:0] fdata;
fid = $fopen("C:/AnyTextFile.txt","rb");
$display("fid = %0d",fid);
if (fid) begin
$display("About to $fread");
if (`failure_1) begin
reg [7:0] fdat;
// This will fail during simulation with:
// FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it // cannot recover. Process will terminate.
cnt = $fread(fdat,fid);
end else if (`failure_2) begin
// This will fail during elaboration with:
// ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
cnt = $fread(fdata,fid);
end else begin
// This will allow the simulation to run and generate clocks on a waveform.
$display("cnt = %0d",cnt);
end else begin
$display("Could not open file");
The file opens as I get a reasonable fid displayed. (I also know the file exists and it constains byte data.) But if I do an fread with a class variable I get one catastrophic failure, if I do an fread with a local variable I get a different catastrophic failure, and if I don't fread the entire simulation works fine.
This is the program code:
program automatic testbench (
input bit clk,
output bit rst_n
data = new();
rst_n = 0; repeat(10) @(posedge clk);
rst_n = 1;
repeat(10) @(posedge clk);
This should be simple but I just cannot work out what's going wrong. This code works fine with other simulators but maybe they're just more forgiving on an error I'm making. Any ideas?
I have attached a file with the entire code. But I had to rename testcase.sv to testcase.txt to make the uploader happy!
06-04-2019 11:03 PM
I gave it a try in 2017.4 but didn't reproduce the crash.
xvlog -sv testbensh.sv
xelab --debug typical -s top work.top
xsim% run -all
fid = -20000
About to $fread
cnt = 0
$finish called at time : 20 ns : File "xxx/sv_fread/testcase.sv" Line 86
06-05-2019 10:55 AM
Thanks for ginving it a try but you executed the path that does not do the fread and therefore demonstrates the test completes cleanly when no fread is done.
I should have been more clear. In the full code I uploaded, testase.txt, there are two defines at the top:
`define failure_1 0 // set both to 0 or one of them to 1
`define failure_2 0
When both are set to 0, no fread will occur and the test will succeed.
When failure_1 is set to 1, fread will attempt put the red data into a local variable but the simulation will fail with "FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate."
When failure_2 is set to 1, fread will attempt put the red data into a class variable but the simulation will fail during elaboration with "ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received."
Sorry for my lack of clarity.
06-05-2019 06:43 PM
Thank you for the clarification.
Yes, I can now reproduce the failures. I gave it a try in Questasim 10.7c.
When macro failure_1 is set to 1, simulation works.
When macro failure_2 is set to 1, I received the below error.
** Error (suppressible): (vsim-PLI-3068) $fread : Invalid argument.
# Time: 0 ps Iteration: 0 Region: /testcase_sv_unit::ProcessData::new File: xxx/testcase.sv Line: 61
# Error loading design
You mentioned it works in other simulators. Did you suppress the error?
06-05-2019 07:55 PM
Graces, I am running the simulation built into Vivado 2017.4 and you get different results from your simulator. For me, failure_1 or _2 set to to one causes a failure. The Cadence ies simulator has no failure. But that could be because there's something about fread I don't know and Cadence is just covering my error. That being said, I have no idea why either of the failing cases are failing cases. Why did the failure you get occur? The class variables should already exit when the new() function exits so it should matter if the operand to fread is a class variable or a local variable.
06-05-2019 11:10 PM
I had a try in VCS. Enabling either failure_1 or failure_2 allows simulaiton to pass.
I'll file a CR against Vivado Simulator with the test case.
06-06-2019 03:41 PM
Thanks Grace. Assuming this results in a change to the simulator in Vivado, will I be able to get the fix? The reason I'm running 2017.4 is because that the latest version I'm licensed to run - the license was part of the VC-709 evaluaton kit.
06-10-2019 06:10 PM
Generally the fix will be integrated to the next Vivado release, probably 2019.2. I'm afraid it will not be put in the old release.
08-06-2019 02:05 PM
Do we have a status on this fread issue? My simulations have come to halt regarding resolution of this issue.