cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
11,490 Views
Registered: ‎02-04-2013

Vivado simulator - strange error

Jump to solution

Hello everybody,

 

I am trying to simulate my design, but the simulator returns some strange error, which doesn't tell me much:

 

[VRFC 10-664] expression has 28 elements : expected 32 [/wrk/2015.3/nightly/2015_09_28_1368829/data/vhdl/src/unisims/primitive/SIM_CONFIGE2.vhd:374]

[XISIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

The design can be implemented and runs on the fpga, so i assume there are no syntax errors in my code.

 

Any idea what could be the problem.

 

Regards

Klemen

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
20,920 Views
Registered: ‎02-04-2013

Re: Vivado simulator - strange error

Jump to solution

I see, thank you,

 

What i found was:signal idcode_reg1  : v32_a (3 downto 0) := (others => TO_STDLOGICVECTOR(DEVICE_ID));

 

It seems the problem is my ICAPE2_inst:

ICAPE2_inst : ICAPE2
    generic map ( DEVICE_ID => X"3651093", ICAP_WIDTH => "X32", SIM_CFG_FILE_NAME => "None" )
    port map (
        O => icap_o_swapped,    -- 32-bit output: Configuration data output bus
        CLK => icap_clk_manual, -- 1-bit input: Clock Input
        CSIB => icap_ce,        -- 1-bit input: Active-Low ICAP Enable
        I => icap_i_swapped,    -- 32-bit input: Configuration data input bus
        RDWRB => icap_write     -- 1-bit input: Read/Write Select input (RDWR_B = 0: Write control, RDWR_B = 1: Read control)
    );

This is a copy of vhdl instantiation template in UG768. Then I changed the DEVICE_ID => X"3651093" to DEVICE_ID => X"03651093" and error was gone. :)

 

Thank you for your help,

Regards

Klemen

 

 

 

 

View solution in original post

0 Kudos
9 Replies
Highlighted
Moderator
Moderator
11,487 Views
Registered: ‎06-24-2015

Re: Vivado simulator - strange error

Jump to solution

Hi @fogl,

This happens when there is a mismatch between the parameters that you have provided and the parameters that have been coded in the primitive. I think you can bring this error down to a warning.

Also, please post your code here.

Thanks,
Nupur
------------------------------------------------------------------------------------------------
Give kudos if it led you to the solution, accept as solution if it resolved your query.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
0 Kudos
Highlighted
Moderator
Moderator
11,479 Views
Registered: ‎07-01-2015

Re: Vivado simulator - strange error

Jump to solution

Hi @fogl,

 

Just have some doubts.

Are you declaring any data type of higher length and assigning it to a lower length datatype?

for e.g;

a: signal std_logic_vector (31 downto 0);

b: signal std_logic_vector (27 downto 0);

b<='1' & a;

 

Which Vivado version you are using?

Can you please check with Vivado 2015.3 and let us know.

Is it an error or warning message?

Are you getting any error in simulation?

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Moderator
Moderator
11,459 Views
Registered: ‎07-21-2014

Re: Vivado simulator - strange error

Jump to solution

@fogl

 

Looks like width mismatch assignment to me, check RTL if any top-level generic is changing the width of the statement signals.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

0 Kudos
Highlighted
Moderator
Moderator
11,447 Views
Registered: ‎01-16-2013

Re: Vivado simulator - strange error

Jump to solution

@fogl,

 

Which vivado version are you using? Also does your project contain Mixed lanuage (verilog and VHDL) coding?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Explorer
Explorer
11,434 Views
Registered: ‎02-04-2013

Re: Vivado simulator - strange error

Jump to solution

I am using Vivado 2015.3. The simulation is set to mixed. My stimulus and also the code is written in vhdl. I think i had to select mixed because BRAM simulation model is written in verilog.

 

SIM_CONFIGE2.vhd that error points to was not written by me.

 

It could be that i am declaring data type of higher length and assigning it to a lower length datatype as suggested (a: signal std_logic_vector (31 downto 0); b: signal std_logic_vector (27 downto 0); b<='1' & a;) but i can not see/find where - the message does not pinpoint to any line in my code. It also seems strange that the design can be implemented and programmed to fpga - this is why i assumed no syntax errors.

 

This is a larger project with several files. I have no idea which part of the code could cause this - i assume the whole code would not help.

0 Kudos
Highlighted
Explorer
Explorer
11,426 Views
Registered: ‎04-28-2015

Re: Vivado simulator - strange error

Jump to solution

Hi @fogl

 

Please post SIM_CONFIGE2.vhd, since the error message points to this file, line 374 as stated in:
 /wrk/2015.3/nightly/2015_09_28_1368829/data/vhdl/src/unisims/primitive/SIM_CONFIGE2.vhd:374

 

This will enable us to review the possible width mismatch.

 

Regards,

Tushar

 

 

0 Kudos
Highlighted
Explorer
Explorer
11,415 Views
Registered: ‎02-04-2013

Re: Vivado simulator - strange error

Jump to solution

Hello,

 

I tried to find this file, but it seems it is not there. I can not even find the folder "wrk".

 

I am using linux.

find / -name "wrk" -type d

find / -name "nightly" -type d

returns nuthing.

0 Kudos
Highlighted
Moderator
Moderator
11,410 Views
Registered: ‎06-24-2015

Re: Vivado simulator - strange error

Jump to solution
Hi @fogl,

Try to look for the file in this folder:
C:\Xilinx\Vivado\2015.3\data\vhdl\src\unisims\primitive

Thanks,
Nupur
Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
0 Kudos
Highlighted
Explorer
Explorer
20,921 Views
Registered: ‎02-04-2013

Re: Vivado simulator - strange error

Jump to solution

I see, thank you,

 

What i found was:signal idcode_reg1  : v32_a (3 downto 0) := (others => TO_STDLOGICVECTOR(DEVICE_ID));

 

It seems the problem is my ICAPE2_inst:

ICAPE2_inst : ICAPE2
    generic map ( DEVICE_ID => X"3651093", ICAP_WIDTH => "X32", SIM_CFG_FILE_NAME => "None" )
    port map (
        O => icap_o_swapped,    -- 32-bit output: Configuration data output bus
        CLK => icap_clk_manual, -- 1-bit input: Clock Input
        CSIB => icap_ce,        -- 1-bit input: Active-Low ICAP Enable
        I => icap_i_swapped,    -- 32-bit input: Configuration data input bus
        RDWRB => icap_write     -- 1-bit input: Read/Write Select input (RDWR_B = 0: Write control, RDWR_B = 1: Read control)
    );

This is a copy of vhdl instantiation template in UG768. Then I changed the DEVICE_ID => X"3651093" to DEVICE_ID => X"03651093" and error was gone. :)

 

Thank you for your help,

Regards

Klemen

 

 

 

 

View solution in original post

0 Kudos