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Observer zxvc
Observer
1,789 Views
Registered: ‎12-31-2007

Vivado simulator v2017.4 crashes with clocking block

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My environment:

Windows 10 Enterprise 64-bit build 16299.125

Vivado v2017.4 (64-bit)

 

I run the behavioral simulation with Vivado simulator with the testbench:

 

`timescale 1ns / 1ps
module tb();
    logic a;
    logic clk;

    initial begin
        clk = 0;
        forever #50 clk = !clk;
    end
    
    clocking cb@(posedge clk);
        input a; 
    endclocking
        
    logic b;
    assign b = cb.a;
    
endmodule

Unfortunately, the simulation crashed and I got these error messages:

launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/git/v/project_1.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/git/v/project_1.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L xil_defaultlib -prj tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/git/v/project_1.srcs/sim_1/new/tb.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/git/v/project_1.sim/sim_1/behav/xsim'
Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto 6661f0fc648148f396768c0ec3e11ff9 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_behav xil_defaultlib.tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
Printing stacktrace...

[0] (KiUserExceptionDispatcher+0x2e) [0x7ffc2eee3b6e]
[1] (ISIMC::VlogCompiler::transform+0x4ec58) [0x7ff7a5ce9988]
[2] (ISIMC::VlogCompiler::transform+0x2f10a) [0x7ff7a5cc9e3a]
[3] (Verific::VeriVisitor::Visit+0x48) [0x7ffbb4fd1ec8]
[4] (Verific::VeriVisitor::TraverseArray+0x49) [0x7ffbb4fced99]
[5] (Verific::VeriVisitor::Visit+0x73) [0x7ffbb4fcfec3]
[6] (Verific::VeriVisitor::TraverseArray+0x49) [0x7ffbb4fced99]
[7] (Verific::VeriVisitor::Visit+0x78) [0x7ffbb4fd1a58]
[8]  [0x7ff7a5c19a61]
[9]  [0x7ff7a5c29282]
[10]  [0x7ff7a5c27dca]
[11] (ISIMC::Options::parseVlogcompCommandLine+0xa9a019) [0x7ff7a6940c09]
[12] (BaseThreadInitThunk+0x14) [0x7ffc2e4e1fe4]

Done
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 855.418 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds
INFO: [USF-XSim-99] Step results log file:'D:/git/v/project_1.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/git/v/project_1.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 855.418 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

Is this a bug of Vivado simulator?

 

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1 Solution

Accepted Solutions
Moderator
Moderator
2,618 Views
Registered: ‎05-31-2017

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

Hi @zxvc,

 

The CR from the thread that you pointed out is of different issue and it has been already fixed in Vivado 2016.3.

The main reason of the crash in your design is the statement

assign b = cb.a;

As per my knowledge I think that the variables of clocking block must be accessed under the initial statement. So, please modify your code as

initial
b = cb.a;

 

This would resolve the issue.

 

Thanks & Regards,
A.Shameer

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9 Replies
1,780 Views
Registered: ‎06-21-2017

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

Is an error shown  in your elaborate.log? 

 

ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/git/v/project_1.sim/sim_1/behav/xsim/elaborate.log' file for more information.
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Observer zxvc
Observer
1,776 Views
Registered: ‎12-31-2007

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

elaborate.log shows:

Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto 6661f0fc648148f396768c0ec3e11ff9 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_behav xil_defaultlib.tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
0 Kudos
1,758 Views
Registered: ‎06-21-2017

Re: Vivado simulator v2017.4 crashes with clocking block

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Have you Googled the error or looked on the forums for the error ? 

XSIM 43-3294

You will find several pages of results.

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Observer zxvc
Observer
1,747 Views
Registered: ‎12-31-2007

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution
0 Kudos
Moderator
Moderator
2,619 Views
Registered: ‎05-31-2017

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

Hi @zxvc,

 

The CR from the thread that you pointed out is of different issue and it has been already fixed in Vivado 2016.3.

The main reason of the crash in your design is the statement

assign b = cb.a;

As per my knowledge I think that the variables of clocking block must be accessed under the initial statement. So, please modify your code as

initial
b = cb.a;

 

This would resolve the issue.

 

Thanks & Regards,
A.Shameer

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Observer zxvc
Observer
1,704 Views
Registered: ‎12-31-2007

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

Thanks, A.Shameer.

 

Synopsys VCS can compile and simulate the code with "assign b = cb.a;." However, I looked up IEEE 1800-2012 standard Chapter 14 and didn't find any example that uses continuous assignment with a clocking variable (clockvar) in right hand side. The standard restricts only that:

"It shall be illegal to write to a variable with a continuous assignment, a procedural continuous assignment, or
a primitive when that variable is associated with an output clockvar."

For example, "assign cb.a = 1" is illegal.

 

Nevertheless, I find a workaround for this problem by using "always_comb." See this example:

`timescale 1ns / 1ps

module tb();
    logic a;
    logic clk;

    initial begin
        clk = 0;
        forever #50 clk = !clk;
    end
    
    clocking cb@(posedge clk);
        input a; 
    endclocking
        
    logic b;
    always_comb begin
        b = cb.a;
    end
    
    initial begin
        a <= 0;
        @(posedge clk);
        a <= 1;
        @(posedge clk);
        $display("a = %d, b = %d", a, b);
        $finish;
    end
    
endmodule

The Vivado Tcl Console will print:

a = 1, b = 0

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Moderator
Moderator
1,677 Views
Registered: ‎09-15-2016

Re: Vivado simulator v2017.4 crashes with clocking block

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Hi @zxvc,

 

Glad to know that you have workaround the issue. Can you please close this thread by marking the post which helped as "accepted solution"

 

Thanks & Regards,

Sravanthi B 

Thanks & Regards,
Sravanthi B
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Moderator
Moderator
1,622 Views
Registered: ‎05-31-2017

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

Hi @zxvc,

 

Just an update. I have filed a CR#995800 and reported this issue(crash) to factory.

 

Thanks & Regards,
A.Shameer

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Observer zxvc
Observer
1,617 Views
Registered: ‎12-31-2007

Re: Vivado simulator v2017.4 crashes with clocking block

Jump to solution

@shameera wrote:

Hi @zxvc,

 

Just an update. I have filed a CR#995800 and reported this issue(crash) to factory.

 

Thanks & Regards,
A.Shameer


Thank you.

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