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Scholar drjohnsmith
Scholar
9,720 Views
Registered: ‎07-09-2009

Vivado : vhdl design impliments fine, but simulator says error in line xxx

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error is

 

ERROR: Array sizes do not match, left array has 8 elements, right array has 6 elements

 

which is true, 

    I made mistake and am assigning a 6 bit unsigned to a 8 bit unsigned 

 

US8 <= US6;

 

should vivado  implimentaoint not pick this up as an error

   were not Verilog, were vhdl.

 

 

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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other thing has come out of this

 

I have now found that one can use Notepad++ as the built in editor of Vivadi, 

 

once you have a project open, its under tools ->options -> general, 

 

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Voyager
Voyager
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Registered: ‎04-21-2014

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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Yes, I agree, it should.  Which version of Vivado are you using?

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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should have said, yes latest version, 2015.2

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-07-2015

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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Hi @drjohnsmith

 

I have tried mismatched assigment of two  signals of UNSIGNED data type.

synthesis is erroring out as expected. (shown below)
Capture.JPG

Can you please make  a test case in which  the mismatched assignment is is getting synthesized properly  and share it here.?

Thanks
Bharath
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Scholar drjohnsmith
Scholar
9,617 Views
Registered: ‎07-09-2009

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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Not easily 

    I can send the archive to Xilinx, 

          but no to an open forum,

 

the archive is 300 K 

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Scholar drjohnsmith
Scholar
9,444 Views
Registered: ‎07-09-2009

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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Ok, 

 

So I have just tried the archive of the code that kept failing yesterday, and today it pass's perfectly.

   i.e. it finds the errors I'd expect.

 

so thats that,

 

BUT

 

it did happen, I showed it to others in the office,

   

Im just wondering, 

   I use the GUI , am jumping in and out of simulatoin and implimentatoin manytimes per hour on the design,

    

and modifying the vhdl files out side the GUI using an external editor,  and files are on multiple machines.

 

I also oftern run sim and implimentation together. ( joys of a small design )

 

I have 'noticed' every 'now and then' the files dont get updated in Vivado GUI for several seconds after I have edited them, 

 

could it be that the testing you do is either on linux, using the in built editor in vivado, all on one machine ?

 

I'm just wondering if the system is working on files in its database / memory , not the ones I have edited a few seconds before . Does one have to wait n seconds after modifying a file before pressing the implimentatoin or sim buttons ?

 

Is there an equivilent of a <ctrl> <F5> one can press to force update , or is it best just to run from TCL.

 

thanks

 

 

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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other thing has come out of this

 

I have now found that one can use Notepad++ as the built in editor of Vivadi, 

 

once you have a project open, its under tools ->options -> general, 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Voyager
Voyager
9,407 Views
Registered: ‎04-21-2014

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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"I'm just wondering if the system is working on files in its database / memory, not the ones I have edited a few seconds before . Does one have to wait n seconds after modifying a file before pressing the implimentatoin or sim buttons ?"

 

Yes, there is a lag time.  You have to wait before Vivado will recognize the file has been modified.

 

And in the case of the simulation, if you modify a source file or testbench, you have to relaunch, not just reset the simulation.

 

And, as you indicated, you can configure vivado to use an external text editor.  Even ones that aren't listed.  I've been checking out Sublime, and also Sigasi, which is a nice editor for VHDL, but way too expensive (but probably worth it if you program advanced VHDL with packages and records).

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Vivado : vhdl design impliments fine, but simulator says error in line xxx

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Thanks Morgan,

 

Have to tell these youngsters the difference between re launching and re seting simulations is an interesting one,

 

esspecialy when vivado sim re coimpiles EVERY THING every time, not just that which has changed.

 

 

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