12-06-2018 01:11 AM - edited 12-06-2018 01:15 AM
Please refer to my prev post: https://forums.xilinx.com/t5/Simulation-and-Verification/xsimk-makes-my-workstation-run-out-of-memory/m-p/906662#M24053
(env details are also mentioned there).
In the above post I had complained that xsimk in Viv2018.2 has a memory leak problem. Given below are the screenshots which show the increase in xsimk memory usage while using Viv2018.2 at increasing simulation intervals (usec).
Support personnel from Xilinx just wanted to have the project (which is impossible to share because of NDA and its sheer huge size, some XY GB), no other help from them.
Others tried to understand the problem and some one told that there might be a problem in my testbench. Still others told that if I am running under Linux this problem might not be there. @drjohnsmith, @richardhead
1. The testbench runs with ModelSim without any problems for days.
2. The next thing I did was to run my design with Vivado 2018.1. I found the same xsimk memory leak problem here too.
3. I then ran my design with Viv2017.4 and yes, here is a stable version of xsimk whose memory usage does not increase with increasing sim time.
This again reiterates the fact that Xilinx is not testing their software products good enough before releasing them. I have lost engineering man-days to find out what the hell was wrong with my testbench. We do not need quarterly software releases, one or two stable and bug-less Vivado release per year is good enough. Yes I know that Vivado Webpack is for free so Xilinx will not spend enough money on testing, but atleast do not introduce new bugs in the existing stable ones!
12-06-2018 01:20 AM
I have NEVER known any software to have no bugs. And with EDA tools the usage combinations are so vast, that they cannot test every combination of code that ever user uses.
Xilinx cannot reproduce your problem without a test case. And so I do not really know what you want Xilinx to do without knowing what the problem is. "There is a memory leak" is a symptom of a bug - not a bug itself.
So yes, this does appear to be a bug in 2018.X, but without help from you - there will be nothing they can do.
While Vivado does tend to be one of the more buggy EDA tools, your latest post is mostly unhelpful.
Provide a test case, or move to another tool.
12-06-2018 01:29 AM - edited 12-06-2018 02:05 AM
I have NEVER known any software to have no bugs
But their test department should be finding this problem. How they are testing it, I don't know. Xilinx is a hugely renowned company and they should have test-cases to catch such problems and expert engineers to debug them.
I have proved that xsimk in 2017.4 is stable than in 2018.x, it is their responsibility to fix them or atleast try to fix them. Why I can't provide a test-case, I have already mentioned.
Provide a test case, or move to another tool.have already mentioned twice.
Yes we will move to ModelSim soon.
In my previous post, "xsimk makes my workstation run out of memory", @xion_pecher, has already provided a test case but there was no response from Xilinx.
12-06-2018 10:09 AM
Well done on working on this,
I dont work for xilinx or any association,
I think one could draw the conclusion that vivado on windows some where get WELL broken,
2018.2 could well go down as Xilinx's "Annus Horribilis "
lets hope the "apparent" delay in getting 2018.3 out, means that they have done some regression testing, fixed some problems,
but more importantly put in place better procedures for the future.
12-07-2018 01:41 AM
lets hope the "apparent" delay in getting 2018.3 out, means that they have done some regression testing, fixed some problems, but more importantly put in place better procedures for the future.