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Visitor
Visitor
92 Views
Registered: ‎05-13-2020

[Vivodo 2019.2][Non-Project Simulation] duplex definition result unexpected

Hi Everyone,

I have a design FDCEx8 as follows,

module FDCEx8(
    input wire [7:0] D,
    input wire E,
    input wire C,
    input wire R,
    output wire [7:0] Q
);

    FDCE #(
        .INIT                   (1'b0),     // Initial value of register, 1'b0, 1'b1
                                            // Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
        .IS_CLR_INVERTED        (1'b0),     // Optional inversion for CLR
        .IS_C_INVERTED          (1'b0),     // Optional inversion for C
        .IS_D_INVERTED          (1'b0)      // Optional inversion for D
    )
    U[7:0] (
        .Q                      (Q[7:0]),   // 1-bit output: Data
        .C                      ({8{C}}),        // 1-bit input: Clock
        .CE                     ({8{E}}),        // 1-bit input: Clock enable
        .CLR                    ({8{R}}),        // 1-bit input: Asynchronous clear
        .D                      (D[7:0])    // 1-bit input: Data
    );
              
endmodule

 

When I call this module in TOP design as follows,

`timescale 1ns / 1ps

module DUT_TOP(
    input wire [7:0] D,
    input wire E,
    input wire C,
    input wire R,
    output wire [7:0] Q
);

    FDCEx8 FDCEx8_U0(
        .D  (D),
        .E  (E),
        .C  (C),
        .R  (R),
        .Q  (Q)
    );

    FDCEx8 FDCEx8_U1(
        .D  (D),
        .E  (E),
        .C  (C),
        .R  (R),
        .Q  (Q)
    );

endmodule

 

When I do the simulation in Vivado 2019.2, the result will be unexpected of Q of FDCEx8.

Here, when I only call one the FDCEx8 module in TOP design, the simulation result will be expected.
But, when I call one the FDCEx8 module two times in TOP design,including FDCEx8_U0 and FDCEx8_U1,
the simulation result will be expected.


For example, when I send D is 8'b0101_1010 to FDCEx8. The Q of FDCEx8 data will be 8'b0zzz_zzzz.
When I only call one the FDCEx8 module in TOP design. The Q of FDCEx8 data will be 8'b0101_1010. 

I don't know what's happened? And the attached file is the project file.

Please help me understand.


Thank you.

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2 Replies
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Xilinx Employee
Xilinx Employee
27 Views
Registered: ‎07-03-2018

Hi,

  Tried with vivado latest version reported issue not observed during simulation.

  Please try with latest vivado version.

Regards,

Ranganath

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Highlighted
Visitor
Visitor
19 Views
Registered: ‎05-13-2020

Hi Rangant,

I'll try the newest version.

When I have any results, I'll report here.

Thank you.

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