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LeonardoVal
Visitor
Visitor
536 Views
Registered: ‎07-16-2021

WARNING:Xst:737 - Found 1-bit latch for signal <memory<58><5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may

HI this is mi first post here i go.

My work is in Xilinx ISE Project Navigator

When i make a behavioral simulation of my design it works perfectly, when i try a Post-Translate simulation the synthesis process bring this warning in almost all the modules and the results are all wrong. Why i get this warning, and how it breaks my design, if it does, and also how do i fix it???

please help me i will attach 1 module so you can see my code

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kdeshwal
Xilinx Employee
Xilinx Employee
458 Views
Registered: ‎11-12-2019

Hi @LeonardoVal ,

If there is a case statement or "if/else" in the code, and if all the possible conditions and states are not covered, a latch is being inferred. This causes the warning message.

- For a case statement, fill up all possible states by using "others" for VHDL or "default" for Verilog.

- For "if/else", ensure that there is an "else" for every "if" so that all cases will be caught.

Check out AR#13979 for your reference.

Thanks,
Kuldeep

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drjohnsmith
Teacher
Teacher
454 Views
Registered: ‎07-09-2009

A latch is a great bit of logic,

   and though we normaly desing with registers, latches do have there place,

The problem is two fold ,

  a) trying to specify timing constraints with latches

  b) most latches are made unintentionally, if you were expecting a register, then the logic will be have different with a latch, give the right input conditions.

 

Of hundreds of logic designs I have done over the decades, I can only think of one case where I had to use a latch, 

    they are that unusual.

I would strongly suggest you do not code for a latch.

 

 

On another note,

   your code is problamatic, and I'd suggest that you get out of these habits now,

Dont use std_logic_arith

     ( have search on line as to why not )

All that "commented out bits" just make the code bulky and less redable

  dont leave in redundant code,

 

Your using variables 

    Its the sort of thing I see in people who are used to writing C,

    Variables are not used very often in VHDL,

      for one thing they just dont behave as you would expect,

    Generally use signals

 

Also, big one

Always remember you are describing the logic that you want to be implimented in the FPAG,

   in theory, especially when you start, you should be able to draw out the logic circuit , gates / registers that you are describing,

      If for something simple you cant do that, then the tools are going to be onto a looser.

 

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LeonardoVal
Visitor
Visitor
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Registered: ‎07-16-2021

Hi 

Sorry for the messy code earlier, i send you the project so you can see it better. I replace all the variables and put signals and the behavioral simulation didnt work because show this:

at 0 ps, Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_3/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

at 0 ps, Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_3/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

at 0 ps, Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_4/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

at 23 ns(1), Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_3/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

at 205 ns(4), Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_4/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

at 1405 ns(5), Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_4/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

at 2815 ns(5), Instance /sm_soc_sm_soc_sch_tb/UUT/XLXI_4/ : Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

 

If you know what could cause this please tell me, the imlementation is supossed to throw 1000 in the three outputs

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LeonardoVal
Visitor
Visitor
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Registered: ‎07-16-2021

Indeed thanks complete the if statements solved the warning in some modules but i have a particular problem to achieve it in the memorization module

Could you tell me another way to make it?? I attached the entire project above but i will ask you about the modifications i made in the memoriation module only

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drjohnsmith
Teacher
Teacher
373 Views
Registered: ‎07-09-2009

Sorry

you seem to be bumping along in the blind,

   please read at least one VHDL book 

even if its

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

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LeonardoVal
Visitor
Visitor
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Registered: ‎07-16-2021

OK thanks, one last question, is any posibility that a great number of latches in a design can cause that the information get lost or something like that??

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drjohnsmith
Teacher
Teacher
302 Views
Registered: ‎07-09-2009

information can never get lost,

  The FPGA performs the system you code for 

   if you code latches, thats what you get 

        if the latches do what you want, and you can work out how to time them, then great

           if the latches do not do what you want, then your system desing is at fault, not the fpga or information,

 

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seamusbleu
Voyager
Voyager
286 Views
Registered: ‎08-12-2008

Your code is clearly trying to describe a RAM, but you don't describe a write clock of any type (or read clock for that matter, but that could be ok if you you are trying to describe a LUTRAM).

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