06-12-2019 04:29 AM - edited 06-12-2019 04:29 AM
I would like tow ait on an internal ready signal in my test bench.
So like this
wait on sys_test.DFT_READY until sys_test.DFT_READY='1';
where sys_test is the instance name of the UUT and DFT_READY is the relevant signal. However, when I put this line in trhe code it says "Illegal selected name prefix". What am I doing wrong?
06-12-2019 12:49 PM
First of all, in your example, wait on is not needed, you can simply use wait until.
This is because you are trying to do an external name verilog style, not VHDL style.
In VHDL, external names are referenced using <<>> and must include an entire signal declaration. So for your example, assuming DFT_READY is a std_logic, you would need:
wait until <<signal sys_test.DFT_READY : std_logic >> = '1';
Obviously this can little long winded, and cumbersum if you need the same signal in multiple places, so usually its best to use an alias:
alias a_DFT_READY is << signal sys_test.DFT_READY : std_logic >>;
wait until a_DFT_READT = '1';
Caveat here is that sys_test must be visible, ie. the alias is declared after the sys_test instantiation.
06-13-2019 03:08 AM - edited 06-13-2019 03:08 AM
06-13-2019 03:10 AM