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Visitor luzhandr
Visitor
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Registered: ‎05-10-2019

Wait for internal signal?

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I would like tow ait on an internal ready signal in my test bench.

So like this

wait on sys_test.DFT_READY until sys_test.DFT_READY='1';

where sys_test is the instance name of the UUT and DFT_READY is the relevant signal. However, when I put this line in trhe code it says "Illegal selected name prefix". What am I doing wrong?

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Scholar richardhead
Scholar
218 Views
Registered: ‎08-01-2012

Re: Wait for internal signal?

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Are you set to VHDL 2008? external names are not available previously.

Can you post the whole code?

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Scholar richardhead
Scholar
229 Views
Registered: ‎08-01-2012

Re: Wait for internal signal?

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First of all, in your example, wait on is not needed, you can simply use wait until.

This is because you are trying to do an external name verilog style, not VHDL style.

In VHDL, external names are referenced using <<>> and must include an entire signal declaration. So for your example, assuming DFT_READY is a std_logic, you would need:

wait until <<signal sys_test.DFT_READY : std_logic >> = '1';

Obviously this can little long winded, and cumbersum if you need the same signal in multiple places, so usually its best to use an alias:

alias a_DFT_READY is << signal sys_test.DFT_READY : std_logic >>;
...
wait until a_DFT_READT = '1';

Caveat here is that sys_test must be visible, ie. the alias is declared after the sys_test instantiation.

Visitor luzhandr
Visitor
224 Views
Registered: ‎05-10-2019

Re: Wait for internal signal?

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Alias doesn't work. It says

[HDL 9-806] Syntax error near "<". 

I put it in the stimuli process before "begin".

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Scholar richardhead
Scholar
219 Views
Registered: ‎08-01-2012

Re: Wait for internal signal?

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Are you set to VHDL 2008? external names are not available previously.

Can you post the whole code?

Visitor luzhandr
Visitor
183 Views
Registered: ‎05-10-2019

Re: Wait for internal signal?

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Yes that is the reason, although this thread tells that VHDL 2008 is switched on permanntly since 2016.x and I have 2018.3

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Scholar richardhead
Scholar
178 Views
Registered: ‎08-01-2012

Re: Wait for internal signal?

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@luzhandr 

Its been available to use, but the user still has to specify 2008 for each file . 2002 is the default mode when reading VHDL

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