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zhi_kaan_zhi
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Registered: ‎05-31-2016

Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL 000 to DSP48E1 instance is invalid.

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Hello, I'm building a large project and I'm using Vivado HLS 2016.1 and my target device Zynq ZC706. When I'm trying to simulate my design with C/RTL Co-Simulation the console keeps showing the following warning:

 

Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.

Time: 6295685 ns Iteration: 11 Process: /apatb_dev_nonbonded_slow_energy_top/AESL_inst_dev_nonbonded_slow_energy/dev_nonbonded_slow_energy_faddfsub_32ns_32ns_32_4_full_dsp_U65/dev_nonbonded_slow_energy_ap_faddfsub_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc File: C:\Xilinx\Vivado\2016.1\data/vhdl/src/unisims/primitive/DSP48E1.vhd

 

The C/RTL Co-simulation is very slow and I think that the output of this warning in console makes it even slower.

Can anyone help me understand this warning and how will I make it disappear?

 

I've attached a printscreen.

 

Thank you in advance.

 

P.S. I'm simulating my design about 20 hours and the console keeps spamming this warning.

 

printscreen.png

1 Solution

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kostas23
Adventurer
Adventurer
14,351 Views
Registered: ‎04-12-2016

Yes I think it shows up in both OS. But you can just ignore it. Nobody knows what it really is, but it works.

View solution in original post

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36 Replies
muzaffer
Teacher
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Registered: ‎03-31-2012
Assuming your C simulation passes, the only conclusion I can draw from your result is that there is something wrong with the code 2016.1 generates which is driving an unknown value into the dsp48 which is the source of your problem.
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zhi_kaan_zhi
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Registered: ‎05-31-2016

Thank you for your reply. So there is nothing I can do, right?

muzaffer
Teacher
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Registered: ‎03-31-2012
I'd suggest trying your design with a different version of Vivado ie 2015.4 ?
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zhi_kaan_zhi
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Registered: ‎05-31-2016

I've found a thread in a forum about this warning but I don't know how to fix it.

 

In the reply he suggests the following:

"Origin of this message is uninitialized value of input (control) signal of DSP component. Such warnings can be ignored at simulation time = 0 ns or few clock cycles later. If this message appear through and through then it's error which must be fixed.
To remove this warning set initial value for reported signal."

 

Does anyone know how to set this initial value?

 

The thread is the following:

http://www.edaboard.com/thread179587.html

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xy0
Visitor
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15,318 Views
Registered: ‎08-24-2016

Same thing happens to me here, in Vivado HLS 2016.4.

 

Hope someone give some help or information. Thanks!!!!

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derickshi
Adventurer
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Registered: ‎11-25-2015

@zhi_kaan_zhi @xy0 I'm having the same problem here. Did you guys solve this?

 

Thanks!

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delk
Observer
Observer
14,921 Views
Registered: ‎02-05-2014

Exact same problem here on Vivado 2016.4 during co-simulation. Anyone managed to fix that?

 

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arpansur
Moderator
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14,910 Views
Registered: ‎07-01-2015

Hi @delk,

 

Are you using VHDL for cosimulation? If so can you please give it a try with Verilog?

Thanks,
Arpan
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delk
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Registered: ‎02-05-2014
I am using Verilog for cosim, but I'll give it a go with VHDL and report back.
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delk
Observer
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Registered: ‎02-05-2014

Same warning with VHDL cosim with only difference the iteration is now 13 (was 11-12 in Verilog cosim).

 

Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 2280755 ns  Iteration: 13  Process: /apatb_triangulate2D_top/AESL_inst_triangulate2D/grp_insertSite_fu_72/grp_inTriangle_fu_364/grp_ccw_fu_69/grp_triArea_fu_56/triangulate2D_fsubkb_U2/triangulate2D_ap_fsub_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /wrk/2016.4/nightly/2017_01_23_1756540/data/vhdl/src/unisims/primitive/DSP48E1.vhd

I am really stuck here! Any ideas?

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aayushntu
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Registered: ‎09-11-2016

Hi,

 

Is this post solved? I am facing this issue with Vivado 2016.4.

I read the suggestion some where that all the variables should be initialized. It allows the co-simulation to pass. However, when I export the IP to Vivado I get faulty results i.e. the IP core does not work as expected. I use chipscope to analyse the results. I suspect the problem is still due to this warning.

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gaucho253
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Registered: ‎03-16-2017

@aayushntu, I currently have the same warning in my 2016.2 design with the simulation remaining in iterations 11 and 12.  I learned that it is not a critical warning, and the co-simulation is still able to complete if you give it enough time.  

 

My design in particular has pointer inputs with large depth values.  It takes multiple days for co-simulation to complete, but I don't know yet if it is the design's fault or the warning's.  I have not exported the IP to Vivado yet.

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Anonymous
Not applicable
12,758 Views

Hi All,

 

I am facing same issue and I ended up following this link. Those who had same issue and came up with solution, mention the way you fixed it. I used Verilog for co-simulation in Vivado2016.2 and the VHDL code of DSP481 in Vivado/2016.2/SDSoC is being called, from where this Warning is coming up.

 

Any suggestions are highly welcomed.

 

Thanks

Divya

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gaucho253
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Registered: ‎03-16-2017

@Anonymous,

 

I receive this warning in 2016.2, but my simulation is still able to complete.  I have not performed a hardware test yet.

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Anonymous
Not applicable
12,739 Views

Hi gaucho,

 

The co-simulation is being on run for 24 hours now. (After looking at your previous post I gave it a try to run longer). Still the same warning is coming up. Any fix you made when your encountered the problem..

 

Thanks

Divya

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gaucho253
Visitor
Visitor
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Registered: ‎03-16-2017

@Anonymous

 

No, I did not make any change to my design regarding this warning because I don't know what causes it.  I also don't know if my long simulation time is related to this warning or not.  

 

In my top level interface, I have a few AXI master inputs and outputs with depth=5000 each (width of 24-32).  Are you also using deep AXI master ports?

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manujvk
Visitor
Visitor
11,641 Views
Registered: ‎05-17-2017

I'm facing the same problem and cosimulation has been running for more than 24 hrs. Is there any solution to it?

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jehandad
Participant
Participant
11,544 Views
Registered: ‎06-08-2016

Vivado HLS version 2017.2 and the error is still there! 

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angu_sewa
Observer
Observer
11,141 Views
Registered: ‎07-16-2017

Does this warning shows up while working with vivado HLS in Linux OS too??

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kostas23
Adventurer
Adventurer
14,352 Views
Registered: ‎04-12-2016

Yes I think it shows up in both OS. But you can just ignore it. Nobody knows what it really is, but it works.

View solution in original post

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polyee13
Explorer
Explorer
9,951 Views
Registered: ‎11-28-2011

Same issue here with 2017.2 on Linux

 

"OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL 000 to DSP48E1 instance is invalid."

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lannylian
Visitor
Visitor
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Registered: ‎12-01-2017

Same issue here with 2017.2 on Linux

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gsutter
Contributor
Contributor
9,205 Views
Registered: ‎10-27-2009

Same error in SDx 2017.2 in Linux. Cosimulating in VHDL and Verilog.

More strange the Latency reported is not the same...

Report: 2917; VHDL: 5399 and Verilo 5428.

The simple algorithm implemented uses Floating Point

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jeff.su
Observer
Observer
8,871 Views
Registered: ‎05-02-2018

Same issue here with Vivado HLS version 2017.2 on Windows

Warning: OPMODE Input Warning : The OPMODE 001XXXX with CARRYINSEL  000 to DSP48E1 instance is invalid.

 

If it's a non-vital warning, is there any method to eliminate the warning message to speed up the co-simulation process??

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pmousoul
Explorer
Explorer
7,663 Views
Registered: ‎05-21-2017

Hello,

 

I'm using SDSoC 2017.2 and I'm trying to co-simulate a floating-point design using as board the zc706.

I get the OPMODE Input Warning and I have the feeling that the simulation does not progress.. it's been 22 hours up to now. The same fixed-point version design simulates at about 20 minutes.

 

Is there any hope, or the only way to check my design is to actually have a zc706 board?

 

Without proper software tools the hardware is unusable no matter how good and well designed it is.

 

 

Cheers,

Panos

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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pmousoul
Explorer
Explorer
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Registered: ‎05-21-2017


After 1469m52.274s c/rtl co-simulation failed!

I have to wait ONE DAY AND ONE HOUR for the cosim to complete.

Still, I have no idea what went wrong.. my fixed-point design works fine (same code) and csim says my design gives correct results.

So, any suggestions?

 

 

Cheers,

Panos

Without proper software tools the hardware is unusable no matter how good and well designed it is.
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agailey
Explorer
Explorer
7,600 Views
Registered: ‎02-08-2018

I had the same problem.  This error showed up and RTL cosimulation was taking a very long time.

 

When configuring RTL cosimulation, select "Setup Only".  That worked for me.  This option makes RTL cosimulation just generate the files.

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nanson
Explorer
Explorer
7,574 Views
Registered: ‎08-31-2017

@agailey

Hi, agailey,
 
Thanks for your reply in the question thread and I just encountered the same problem. However, I have a question for you.
 
For the "Setup Only" option you mentioned, what's the purpose while set it ? Does it still run the C/RTL co-sim but not shown the progress and logging on the console screen ? Or it doesn't run C/RTL co-sim ? 
 
p.s. I use Vivado HLS/Vivado 2017.2 
 
Many thanks in advance.

 

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agailey
Explorer
Explorer
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Registered: ‎02-08-2018

@nansonThe "Setup Only" option does seem to allow co-sim to run. I have the test bench print the results to the screen at runtime, and I do see these results printed to the screen even when "Setup Only" is selected.

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