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Newbie hlyxilinx
Newbie
221 Views
Registered: ‎08-12-2019

Warning: Uninitialize out port ../../u0_clk_wiz/clk_out1 has not driver

Hi,

u0_clk_wiz is clock generated by the Vivado IP tool,  I already compile the unisim lib, but still have this warning, which result in my clk_out1 has not output.

thanks

 

 

 

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Xilinx Employee
Xilinx Employee
191 Views
Registered: ‎07-16-2008

回复: Warning: Uninitialize out port ../../u0_clk_wiz/clk_out1 has not driver

How did you launch the simulation? From within Vivado IDE or command line using your own script?

If you're using Vivado Simulator, you don't have to compile simulation libraries. They're pre-compiled in the install area.

Can you attach the test case to demonstrate the problem?

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Newbie hlyxilinx
Newbie
163 Views
Registered: ‎08-12-2019

回复: Warning: Uninitialize out port ../../u0_clk_wiz/clk_out1 has no driver

I used Modelsim PE as my simulation tool.

 

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Xilinx Employee
Xilinx Employee
148 Views
Registered: ‎07-16-2008

回复: Warning: Uninitialize out port ../../u0_clk_wiz/clk_out1 has no driver

It's not likely related to library compilation.

Without a test case, it's hard to say what is wrong here. The "clk_out1" is one of the Clocking Wizard IP output ports and shouldn't be undriven. You may want to check the connections in RTL.

If you want further investigation, please attach the design and steps to reproduce the issue. 

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