08-12-2019 05:37 PM
u0_clk_wiz is clock generated by the Vivado IP tool, I already compile the unisim lib, but still have this warning, which result in my clk_out1 has not output.
08-13-2019 12:07 AM
How did you launch the simulation? From within Vivado IDE or command line using your own script?
If you're using Vivado Simulator, you don't have to compile simulation libraries. They're pre-compiled in the install area.
Can you attach the test case to demonstrate the problem?
08-14-2019 07:32 PM
It's not likely related to library compilation.
Without a test case, it's hard to say what is wrong here. The "clk_out1" is one of the Clocking Wizard IP output ports and shouldn't be undriven. You may want to check the connections in RTL.
If you want further investigation, please attach the design and steps to reproduce the issue.