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Adventurer
Adventurer
8,455 Views
Registered: ‎12-17-2014

Warnings after post synthesis simulation

i am using vertex-5 fpga,before post syntheis simulation i am getting correct simulation result but after post syntheis simulation and place and routing i am not getting any simulation result.

GIVEN BELOW WARNINGS ARE THE..HOW TO REMOVE THESE FLAW. For eg. for j0 i gave 8 bit signal in my code..but why it is showing actual width is 12 bit. and same for rest of the warnings.

 

 

ISim P.58f (signature 0x7708f090)
This is a Full version of ISim.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j0 is not equal to width 8 of actual signal j0.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j1 is not equal to width 8 of actual signal j1.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j2 is not equal to width 8 of actual signal j2.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j3 is not equal to width 8 of actual signal j3.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j4 is not equal to width 8 of actual signal j4.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j5 is not equal to width 8 of actual signal j5.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j6 is not equal to width 8 of actual signal j6.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 23.  For instance uut/m/, width 12 of formal port j7 is not equal to width 8 of actual signal j7.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/m/, width 13 of formal port f0 is not equal to width 9 of actual signal f0.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/m/, width 13 of formal port f1 is not equal to width 9 of actual signal f1.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/m/, width 13 of formal port f2 is not equal to width 9 of actual signal f2.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/m/, width 13 of formal port f3 is not equal to width 9 of actual signal f3.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/m/, width 13 of formal port a is not equal to width 9 of actual signal z0.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/m/, width 13 of formal port z1 is not equal to width 9 of actual signal z1.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/m/, width 13 of formal port z2 is not equal to width 9 of actual signal z2.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/m/, width 13 of formal port z3 is not equal to width 9 of actual signal z3.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/w/, width 13 of formal port x0 is not equal to width 9 of actual signal f0.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/w/, width 13 of formal port x1 is not equal to width 9 of actual signal f1.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/w/, width 13 of formal port x2 is not equal to width 9 of actual signal f2.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 27.  For instance uut/w/, width 13 of formal port x3 is not equal to width 9 of actual signal f3.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 24.  For instance uut/w/, width 16 of formal port y0 is not equal to width 13 of actual signal r0.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 24.  For instance uut/w/, width 16 of formal port y1 is not equal to width 13 of actual signal r2.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 24.  For instance uut/w/, width 16 of formal port y2 is not equal to width 13 of actual signal r4.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 24.  For instance uut/w/, width 16 of formal port y3 is not equal to width 13 of actual signal r6.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/e0/, width 13 of formal port z0 is not equal to width 9 of actual signal z0.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e0/, width 14 of formal port s018 is not equal to width 11 of actual signal s018.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e0/, width 14 of formal port s050 is not equal to width 11 of actual signal s050.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e0/, width 14 of formal port s075 is not equal to width 11 of actual signal s075.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e0/, width 14 of formal port s089 is not equal to width 11 of actual signal s089.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/e1/, width 13 of formal port z1 is not equal to width 9 of actual signal z1.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e1/, width 14 of formal port s118 is not equal to width 11 of actual signal s118.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e1/, width 14 of formal port s150 is not equal to width 11 of actual signal s150.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e1/, width 14 of formal port s175 is not equal to width 11 of actual signal s175.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e1/, width 14 of formal port s189 is not equal to width 11 of actual signal s189.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/e2/, width 13 of formal port z2 is not equal to width 9 of actual signal z2.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e2/, width 14 of formal port s218 is not equal to width 11 of actual signal s218.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e2/, width 14 of formal port s250 is not equal to width 11 of actual signal s250.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e2/, width 14 of formal port s275 is not equal to width 11 of actual signal s275.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e2/, width 14 of formal port s289 is not equal to width 11 of actual signal s289.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 28.  For instance uut/e3/, width 13 of formal port z3 is not equal to width 9 of actual signal z3.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e3/, width 14 of formal port s318 is not equal to width 11 of actual signal s318.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e3/, width 14 of formal port s350 is not equal to width 11 of actual signal s350.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e3/, width 14 of formal port s375 is not equal to width 11 of actual signal s375.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 26.  For instance uut/e3/, width 14 of formal port s389 is not equal to width 11 of actual signal s389.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 25.  For instance uut/q/, width 16 of formal port r1 is not equal to width 13 of actual signal r1.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 25.  For instance uut/r/, width 16 of formal port r3 is not equal to width 13 of actual signal r3.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 25.  For instance uut/s/, width 16 of formal port r5 is not equal to width 13 of actual signal r5.
WARNING: File "F:/xillinx program/dct_8/dct.v" Line 25.  For instance uut/t/, width 16 of formal port r7 is not equal to width 13 of actual signal r7.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 39.  For instance dct_tb/uut/, width 13 of formal port r0 is not equal to width 11 of actual signal r0.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 40.  For instance dct_tb/uut/, width 13 of formal port r1 is not equal to width 11 of actual signal r1.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 41.  For instance dct_tb/uut/, width 13 of formal port r2 is not equal to width 11 of actual signal r2.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 42.  For instance dct_tb/uut/, width 13 of formal port r3 is not equal to width 11 of actual signal r3.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 43.  For instance dct_tb/uut/, width 13 of formal port r4 is not equal to width 11 of actual signal r4.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 44.  For instance dct_tb/uut/, width 13 of formal port r5 is not equal to width 11 of actual signal r5.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 45.  For instance dct_tb/uut/, width 13 of formal port r6 is not equal to width 11 of actual signal r6.
WARNING: File "F:/xillinx program/dct_8/dct_tb.v" Line 46.  For instance dct_tb/uut/, width 13 of formal port r7 is not equal to width 11 of actual signal r7.

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3 Replies
Xilinx Employee
Xilinx Employee
8,435 Views
Registered: ‎07-16-2008

Re: Warnings after post synthesis simulation

Can you post the test case for a look?

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Adventurer
Adventurer
8,427 Views
Registered: ‎12-17-2014

Re: Warnings after post synthesis simulation

module dct_tb;

    // Inputs
    reg clk;
    reg [7:0] j0;
    reg [7:0] j1;
    reg [7:0] j2;
    reg [7:0] j3;
    reg [7:0] j4;
    reg [7:0] j5;
    reg [7:0] j6;
    reg [7:0] j7;

    // Outputs
    wire [10:0] r0;
    wire [10:0] r1;
    wire [10:0] r2;
    wire [10:0] r3;
    wire [10:0] r4;
    wire [10:0] r5;
    wire [10:0] r6;
    wire [10:0] r7;
    
    
    

    // Instantiate the Unit Under Test (UUT)
    dct uut (
        .clk(clk),
        .j0(j0),
        .j1(j1),
        .j2(j2),
        .j3(j3),
        .j4(j4),
        .j5(j5),
        .j6(j6),
        .j7(j7),
        .r0(r0),
        .r1(r1),
        .r2(r2),
        .r3(r3),
        .r4(r4),
        .r5(r5),
        .r6(r6),
        .r7(r7)
        
        
        
        
    );



    initial begin
    
    $monitor ("j0=%d,j1=%d,j2=%d,j3=%d,j4=%d,j5=%d,j6=%d,j7=%d,r0=%b,r1=%b,r2=%b,r3=%b,r4=%b,r5=%b,r6=%b,r7=%b",jo,j1,j2,j3,j4,j5,j6,j7,r0,r1,r2,r3,r4,r5,r6,r7);
        // Initialize Inputs
        clk = 1;
        j0 = 8'd7;
        j1 = 8'd6;
        j2 = 8'd5;
        j3 = 8'd4;
        j4 = 8'd3;
        j5 = 8'd2;
        j6 = 8'd1;
        j7 = 8'd1;

    #10;
    
      clk = 1;
        j0 = 8'd9;
        j1 = 8'd8;
        j2 = 8'd7;
        j3 = 8'd6;
        j4 = 8'd5;
        j5 = 8'd4;
        j6 = 8'd3;
        j7 = 8'd1;
        
    #10;
    $finish;
    end
    
    initial
    begin
    forever #5 clk= ~clk;
    end
      
endmodule

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Moderator
Moderator
8,398 Views
Registered: ‎07-21-2014

Re: Warnings after post synthesis simulation

Hi,

 

Can you post your UUT code also? Looks like the width declared in the UUT is different.

 

Thanks,
Anusheel
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