06-15-2018 06:03 AM
Hi, here's a simple piece of code and the resulting waveform puzzles me a little bit. Please help.
module test_tb; reg a; wire a2, b2, out2; always begin a = 0; #5; a = ~a; #5; end assign a2 = a; assign b2 = 1; and #(5, 7) g2(out2, a2, b2);endmodule
Why red line in the middle?
Why out2 keeps being 1, instead of keeping in line with a2, after 10 time units (as I measure)?
How does #(5, 7) work?
06-18-2018 04:44 AM - edited 06-18-2018 04:44 AM
I believe that it is a rsie fall time setting e.g. from the language reference manual:
or #(4, 3) ig (o, a, b); /* or gate called ig (instance name); rise time = 4, fall time = 3 */
06-18-2018 09:53 PM
As specified by @amaccre, those delays correspond to the gate level delays.
In general, it has three delays Rise, fall and turnoff.
The rise delay is a delay with a gate output transition to 1 from other values (0, x, z).
The fall delay is a delay with a gate output transition to 0 from other values (1, x, z).
The Turn-off delay is a delay with a gate output transition to z from other values (0, 1, x).
If you specify only one delay then it considers same for all Rise, fall and typical.
Ex:- and #1 b2(out2,a2,b2) --> Rise=1, Fall=1, Turnoff=1;
If you specify two delays then it considers for Rise and fall alone.
Ex:- and #(1,2) b2(out2,a2,b2) --> Rise=1, Fall=2;
If you specify three delays then it considers for all Rise, fall and typical delays.
Ex:- and #(1,2,3) b2(out2,a2,b2) --> Rise=1, Fall=2, Turnoff=3;
Thanks & Regards,
10-06-2018 11:57 PM
Yeah, that makes good sense, rise & fall delay.
But I'm still confused as to the red line during the first 10 time units
and the result's remaining unchanged.