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Observer wangxiao@skhms
Observer
731 Views
Registered: ‎10-30-2018

When will Vivado Simulator support Ultrascale+ HBM simulation?

I ran a design example simulation for created HBM IP, in the latest Vivado v2019.1.1 using Vivado Simulator, and failed (xci file is attached). The simulation compelling processing was stopped by the following error messages:

[VRFC 10-2063] Module <axi_protocol_checker_v1_1_top> not found while processing module instance <genblk1.PC> ["c:/FPGA_Designs/.../Vivado/IP/hbm_if_ex/imports/axi_top.sv":394]

Then I was told that the current Vivado Simulator does not support HBM simulation (see PG276, there is not any details about the reasons). It looks very bad for the users who do not have the third party simulator tools.

The above error message shows a missing module definition file, for my understanding, it should not related to what simulator is used? 

When will Vivado Simulator support HBM simulation? I think it is a must fix issue. (The created HBM IP passed synthesis and routing tests.)

Thanks.

XIao

 

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7 Replies
Moderator
Moderator
669 Views
Registered: ‎04-24-2013

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

Hi wangxiao@skhms 

Behavioral simulations using verilog simulation models are supported at this time, but Netlist (post-synthesis and postimplementation) simulations are not supported at this time.

Full simulation support is on the roadmap but there is currently no timeframe that I am aware of.

The following Answer Record will contain the most up to date information as it is released

https://www.xilinx.com/support/answers/69267.html

Best Regards
AIdan

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Participant digitate
Participant
661 Views
Registered: ‎02-06-2018

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

@amaccreis that really true ? i was under the impression that the Vivado simulator does not support even behvioral simulation

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Moderator
Moderator
649 Views
Registered: ‎04-24-2013

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

Hi @digitate ,

This is what is specified in PG276, so I was taking this as correct.

See notes 3 & 4 below.

Best Regards
Aidan

Capture.PNG

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Visitor jie.zhang
Visitor
355 Views
Registered: ‎11-06-2019

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

Hi Xiao,

 

I am encountering the same problem in simulation using vivado simulator, I am wondering how you dealt with this error?

 

Thanks,

 

Jack

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Contributor
Contributor
288 Views
Registered: ‎10-05-2018

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

I get the same error even for behavorial sims:

Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /hwnet/xilinx/vivado/vivado2019.2/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto f66acffdae084e78be488fe12f69c9bb --incr --debug typical --relax --mt 8 -L xil_defaultlib -L hbm_v1_0_5 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sim_tb_top_behav xil_defaultlib.sim_tb_top xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2063] Module <axi_protocol_checker_v1_1_top> not found while processing module instance <genblk1.PC> [/u/alinave/projects/nosara/hbm/behav_model/behav_model_xcvu47p/example/hbm_0_ex/imports/axi_top.sv:394]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

 

Where can we get these missing files for the sims?

Thanks.

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Visitor jie.zhang
Visitor
270 Views
Registered: ‎11-06-2019

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

the same case I encountered
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Moderator
Moderator
130 Views
Registered: ‎11-28-2016

Re: When will Vivado Simulator support Ultrascale+ HBM simulation?

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