07-11-2019 10:31 AM
I ran a design example simulation for created HBM IP, in the latest Vivado v2019.1.1 using Vivado Simulator, and failed (xci file is attached). The simulation compelling processing was stopped by the following error messages:
[VRFC 10-2063] Module <axi_protocol_checker_v1_1_top> not found while processing module instance <genblk1.PC> ["c:/FPGA_Designs/.../Vivado/IP/hbm_if_ex/imports/axi_top.sv":394]
Then I was told that the current Vivado Simulator does not support HBM simulation (see PG276, there is not any details about the reasons). It looks very bad for the users who do not have the third party simulator tools.
The above error message shows a missing module definition file, for my understanding, it should not related to what simulator is used?
When will Vivado Simulator support HBM simulation? I think it is a must fix issue. (The created HBM IP passed synthesis and routing tests.)
07-16-2019 12:34 AM
Behavioral simulations using verilog simulation models are supported at this time, but Netlist (post-synthesis and postimplementation) simulations are not supported at this time.
Full simulation support is on the roadmap but there is currently no timeframe that I am aware of.
The following Answer Record will contain the most up to date information as it is released
07-16-2019 12:52 AM
07-16-2019 03:47 AM
Hi @digitate ,
This is what is specified in PG276, so I was taking this as correct.
See notes 3 & 4 below.
11-14-2019 12:24 AM
I am encountering the same problem in simulation using vivado simulator, I am wondering how you dealt with this error?
11-21-2019 03:59 PM
I get the same error even for behavorial sims:
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /hwnet/xilinx/vivado/vivado2019.2/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto f66acffdae084e78be488fe12f69c9bb --incr --debug typical --relax --mt 8 -L xil_defaultlib -L hbm_v1_0_5 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sim_tb_top_behav xil_defaultlib.sim_tb_top xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
ERROR: [VRFC 10-2063] Module <axi_protocol_checker_v1_1_top> not found while processing module instance <genblk1.PC> [/u/alinave/projects/nosara/hbm/behav_model/behav_model_xcvu47p/example/hbm_0_ex/imports/axi_top.sv:394]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
Where can we get these missing files for the sims?
12-17-2019 10:17 AM
There are no plans to add Vivado simulator support for the Virtex UltraScale+ HBM IP.
The supported simulators are QuestaSim, VCS, and IES. Refer to UG973 to see the list of supported operating systems and third party simulators for your specific Vivado release.