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Observer cherry_essam
Observer
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Registered: ‎11-10-2018

Why D is always 8'bxxxxxxxx?

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I am trying to implement a 8255 PPI chip and that's the testbench for the PPI module.

The problem is that D(databus) is always 8'bxxxxxxx , it is never assigned to any value ,even though i wrote that if no condition is true D (databus)must be 8'b01zzzzzz .

So could be the assignment line of D never executed? 

and is there a way of debugging in Xilinx to check the execution of every line like in other programs like visual studio?

Please Help :(

-------------------------------------------------------------------------------------------------------------------

module tb();
wire [7:0] portA,portB,portC;
wire[7:0]D;
reg [7:0] input_porta,input_portb,input_portc,input_d;
reg rd,wr,cs,reset,gnd,vcc;
reg[1:0] a;
PPI mytb(portA,portB,portC,D,rd,wr,cs,reset,gnd,vcc,a);

assign portA=(a==2'b00&&!rd)?input_porta:(a==2'b00&&!wr)?8'bzzzzzzzz:1'bz; //port A could be output or input


assign D=(!rd)?8'bzzzzzzzz:(!wr)?input_d:8'b01zzzzzz; //databus

assign portB=(a==2'b01&&!rd)?input_portb:(a==2'b01&&!wr)?8'bzzzzzzzz:1'bz; //port B could be output or input

assign portC[7:4]=(a==2'b10&&!rd)?input_portc[7:4]:(a==2'b10&&!wr)?4'bzzzz:1'bx; //port c upper could be output or input

assign portC[3:0]=(a==2'b10&&!rd)?input_portc[3:0]:(a==2'b10&&!wr)?4'bzzzz:1'bx; //port c lower could be output or input
initial
begin

vcc<=1;gnd<=0;cs<=0;reset<=0;
$monitor("%b %b %b %b %b %b",input_d,portA,vcc,gnd,cs,reset);
#10
a[0]=0; a[1]=0;wr=0;rd=1;input_d=10000011; //to write from databus to port a 

end


endmodule

------------------------------------------------------------------------------------------------------------------------------------

 

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Moderator
Moderator
251 Views
Registered: ‎09-15-2016

Re: Why D is always 8'bxxxxxxxx?

Jump to solution

Hi @cherry_essam

Looks like duplicate post of below. Please avoid posting duplicates.

https://forums.xilinx.com/t5/Simulation-and-Verification/Why-D-is-always-x/td-p/918014

As for your query,

is there a way of debugging in Xilinx to check the execution of every line

You can try setting up breakpoints and step over the lines of code. Please refer the below user guide lab2 step 9 page#41:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug937-vivado-design-suite-simulation-tutorial.pdf

Also, you can turn on line tracing, use one of the following Tcl commands:

ltrace on

set_property line_tracing true [current_sim]

For more information, please refer the below user guide page#107:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug900-vivado-logic-simulation.pdf

To check this issue at our end can you please share the PPI UUT module and the complete test case.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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2 Replies
Moderator
Moderator
252 Views
Registered: ‎09-15-2016

Re: Why D is always 8'bxxxxxxxx?

Jump to solution

Hi @cherry_essam

Looks like duplicate post of below. Please avoid posting duplicates.

https://forums.xilinx.com/t5/Simulation-and-Verification/Why-D-is-always-x/td-p/918014

As for your query,

is there a way of debugging in Xilinx to check the execution of every line

You can try setting up breakpoints and step over the lines of code. Please refer the below user guide lab2 step 9 page#41:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug937-vivado-design-suite-simulation-tutorial.pdf

Also, you can turn on line tracing, use one of the following Tcl commands:

ltrace on

set_property line_tracing true [current_sim]

For more information, please refer the below user guide page#107:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug900-vivado-logic-simulation.pdf

To check this issue at our end can you please share the PPI UUT module and the complete test case.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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Observer cherry_essam
Observer
240 Views
Registered: ‎11-10-2018

Re: Why D is always 8'bxxxxxxxx?

Jump to solution

@bandi 

sorry i thought to make another post as this is a modified code.

sure i will provide the module , i made a testbench for module PortAorPortB only and it worked since all other modules(for port c lower and port c upper) are the same as this module.

Note: i am implementing the chip in mode 0 and BSR mode only

________________________________________________________________________________

module PortAorPortB(inoutright,databus,signal,enable);
inout [7:0] inoutright;
inout [7:0] databus;
input signal;
input enable;
reg [7:0] out1;
always @(*)
begin
if(enable && !signal) out1<=inoutright;
end
assign inoutright=(signal && enable )?8'bzzzzzzzz:(!signal && enable)?databus:(!enable && !signal)?out1:(! enable && signal)?8'bzzzzzzzz:1'bz;
assign databus=(signal && enable)?inoutright:(!signal && enable)? 8'bzzzzzzzz:(!enable && !signal)?8'bzzzzzzzz:(!enable && signal)?inoutright:1'bz;
endmodule
______________________________________________________comment________________________
/*module tb();
wire[7:0] inoutright;
wire [7:0] databus;
reg signal;
reg enable;
reg [7:0] input_to_inoutright;
reg[7:0] input_to_databus;
assign inoutright=(signal && enable)?input_to_inoutright:(!signal && enable)?8'bzzzzzzzz:(!enable && signal)?input_to_inoutright:(!enable && ! signal)?8'bzzzzzzzz:1'bz;
assign databus=(signal && enable)?inoutright:(!signal && enable)?input_to_databus:(!enable &&signal)?8'bzzzzzzzz:(!enable && !signal)?input_to_databus:1'bz;
initial
begin
$monitor("%b %b %b %b ",enable,signal,inoutright,databus);
#15
signal=0;enable=0;input_to_inoutright=8'b1011_1000; input_to_databus=8'b0000_0000;
#15
signal=1;enable=0; input_to_inoutright=8'b1011_1000; input_to_databus=8'b0000_0000;
#15
signal=0;enable=1; input_to_inoutright=8'b1000_0000; input_to_databus=8'b1000_0001;
#15
signal=1; enable=1;input_to_inoutright=8'b1000_0000; input_to_databus=8'b1011_1111;
#15
signal=0; enable=0; input_to_inoutright=8'b0001_0001; input_to_databus=8'b0001_0001;// inoutright must be as previous line //latching//databus =0001_0001


end
PortAorPortB myport(inoutright,databus,signal,enable);
endmodule
//*/
_______________________________________________________end of comment__________________
module PortCUpper(inoutright,databus,signal,enable,bsr);
inout [7:4] inoutright;
inout [7:4] databus;
input signal,bsr;
input enable;
reg [7:4] out1;
always @(*)
begin
if(enable && !signal&&bsr) out1<=inoutright;
end
assign inoutright=(signal && enable&&bsr )?4'bzzzz:(!signal && enable&&bsr)?databus:(!enable && !signal&&bsr)?out1:(! enable && signal&&bsr)?4'bzzzz:(!bsr)?4'bzzzz:1'bx;
assign databus=(signal && enable)?inoutright:(!signal && enable)? 4'bzzzz:(!enable && !signal)?4'bzzz:(!enable && signal)?inoutright:1'bz;
endmodule
module PortCLower(inoutright,databus,signal,enable,bsr);
inout [3:0] inoutright;
inout [3:0] databus;
input signal,bsr;
input enable;
reg [3:0] out1;
always @(*)
begin
if(enable && !signal&&bsr) out1<=inoutright;
end
assign inoutright=(signal && enable&&bsr )?4'bzzzz:(!signal && enable&&bsr)?databus:(!enable && !signal&&bsr)?out1:(! enable && signal&&bsr)?4'bzzzz:(!bsr)?4'bzzzz:1'bx;
assign databus=(signal && enable)?inoutright:(!signal && enable)? 4'bzzzz:(!enable && !signal)?4'bzzz:(!enable && signal)?inoutright:1'bz;
endmodule

 


///////////////PPI///////////////////////
module PPI(portA,portB,portC,D,rd,wr,cs,reset,gnd,vcc,a);
inout [7:0] portA,portB,portC,D; //D is databus
input rd,wr,cs,reset,gnd,vcc;
input [1:0] a;//ao and a1
reg [1:0]x;//for enable and signal (out or in)
reg [1:0]y;
reg [1:0]z;
reg [1:0]w;
reg bsr;
reg [7:0]outc;
reg [7:0] controlword;
PortAorPortB PortA(portA,D,x[0],x[1]);
PortAorPortB PortB(portB,D,y[0],y[1]);
PortCUpper PortC(portC[7:4],D[7:4],z[0],z[1],bsr);
PortCLower PortCl(portC[3:0],D[3:0],w[0],w[1],bsr);
assign portC=(a==2'b11&&D[7]==0)?outc:8'bzzzzzzzz;
always@(*)
begin
if(vcc==1&&gnd==0&&cs==0)
begin
if(reset==1)
begin
x[0]=1;
y[0]=1;
z[0]=1;
w[0]=1;
end
else
begin
case(a)
2'b00:
begin
if(!rd) x<=2'b11;else x<=2'b01;
end
2'b01:
begin
if(!rd) y<=2'b11;else y<=2'b01;
end
2'b10:
begin
if(!rd) begin z<=2'b11;w<=2'b11;end
else begin z<=2'b01;w<=2'b01;end
end
2'b11:
begin
if(!wr) controlword<=D;
end
endcase
if(controlword[7]==0)//BSR
begin
bsr<=0;
outc[controlword[3:1]]<=controlword[0];
end
else //mode 0
begin
if(controlword[2]==0)//group b mode 0
begin
if(controlword[0]==0)//clower
w[0]<=0;
else
w[0]<=1;
if(controlword[1]==0)//port b
y[0]<=0;
else
y[0]<=1;
end
else
begin
z<=2'bzz;
y<=2'bzz;///// mode 1 &2
end
end
if(controlword[6:5]==2'b00)//// mode 0
begin
if(controlword[3]==0)/// c upper
z[0]<=0;
else
z[0]<=1;
if(controlword[4]==0) ///porta
x[0]<=0;
else
x[0]<=1;
end
end

end
end
endmodule

 

 


///////////////////////TESTBENCH///////////////////////////////
module tb();
wire [7:0] portA,portB,portC;
wire[7:0]D;
reg [7:0] input_porta,input_portb,input_portc,input_d;
reg rd,wr,cs,reset,gnd,vcc;
reg[1:0] a;
PPI mytb(portA,portB,portC,D,rd,wr,cs,reset,gnd,vcc,a);

assign portA=(a==2'b00&&!rd)?input_porta:(a==2'b00&&!wr)?8'bzzzzzzzz:1'bz;

___________comment_______________________________________________________

/*assign D=((a==2'b00&&!rd)||(a==2'b01&&!rd)||(a==2'b10&&!rd)||(a==2'b10&&!rd))?8'bzzzzzzzz:
((a==2'b00&&!wr)||(a==2'b01&&!wr)||(a==2'b11 &&!wr ))?input_d:8'b01zzzzzz;*/

____________end of comment__________________________________________________________
assign D=(!rd)?8'bzzzzzzzz:(!wr)?input_d:8'b01zzzzzz;

assign portB=(a==2'b01&&!rd)?input_portb:(a==2'b01&&!wr)?8'bzzzzzzzz:1'bz;

assign portC[7:4]=(a==2'b10&&!rd)?input_portc[7:4]:(a==2'b10&&!wr)?4'bzzzz:1'bx;

assign portC[3:0]=(a==2'b10&&!rd)?input_portc[3:0]:(a==2'b10&&!wr)?4'bzzzz:1'bx;
initial
begin

vcc<=1;gnd<=0;cs<=0;reset<=0;
$monitor("%b %b %b %b %b %b",input_d,portA,vcc,gnd,cs,reset);
#10
a[0]=0; a[1]=0;wr=0;rd=1;input_d=10000011;
//#10
//a<=2'b00;wr<=0;rd=1;d=0001_1111;

end


endmodule

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