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Visitor
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Registered: ‎04-18-2014

Why am I getting theses ERRORS?

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module VendingMach( input clk, input sC,sG,i10, i5, reset,
output Gum, Candy, ch, dSum[6:0] );


reg f5,s5,th5,f10,s10;
output reg candy, gum;
wire f5w,s5w,th5w,f10w,s10w;
assign gum = Gum;
assign candy = Candy;
assign s10w = f10 ;
assign f5w = s5;
assign s5w = th5;
//parameter initialization and nulling!


always @ ( posedge clk )
begin //this part is for candy
if (reset == 1)
begin
f5 <= 0; s5 <= 0; th5 <= 0; f10 <= 0; s10 <= 0;
end
if (sC == 1 )
begin
if (i10 == 1)
begin
f10 = f10 + 1;
if ( (s10 == 1) & (f5 == 1) )
Candy = f5w & s10w;
end
if ( f5 == 1 ) //this part is for 5+5+5+10
begin
f5 = f5 +1;
Candy = f5w & s5w & f10w;
end
end //end of candy probabilities

if (i5 == 1)
begin
f5 = f5 + 1;
if ( ( f5 == 1 ) & ( th5 == 1 ))
Candy = f5w & th5w;
end //end candy design for 5 5s & 2 10s +5
if ( sG ==1)
begin
if ( f5 ==1 ) //this part is for gum
begin
f5 = f5 +1;
Gum = f5w & s5w; //5+5+5
end
Gum = f5w & f10w; //5+10
end //end of Gum probabilities

end

endmodule

 

________________________________________________

 

I am getting the following errors but Why?

 

ERROR:HDLCompiler:329 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 28: Target <gum> of concurrent assignment or output port connection should be a net type.

 

I mean how **bleep** a net type!!! not logical!


ERROR:HDLCompiler:329 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 29: Target <candy> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 48: Procedural assignment to a non-register Candy is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 48: Procedural assignment to a non-register Candy is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 53: Procedural assignment to a non-register Candy is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 53: Procedural assignment to a non-register Candy is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 61: Procedural assignment to a non-register Candy is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 61: Procedural assignment to a non-register Candy is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 68: Procedural assignment to a non-register Gum is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 68: Procedural assignment to a non-register Gum is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 70: Procedural assignment to a non-register Gum is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:1660 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 70: Procedural assignment to a non-register Gum is not permitted, left-hand side should be reg/integer/time/genvar
ERROR:HDLCompiler:598 - "C:\Users\acer\Documents\Xilinx\VendingMachineUpgrade\VendingMach.v" Line 21: Module <VendingMach> ignored due to previous errors.

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Highlighted
Moderator
Moderator
16,117 Views
Registered: ‎04-17-2011

Re: Why am I getting theses ERRORS?

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Modified non-error code:

 

module VendingMach( input clk, input sC,sG,i10, i5, reset,
//set Gum & Candy as outout reg and correct dSum declaration
output reg Gum, output reg Candy, ch, [6:0] dSum );


reg f5,s5,th5,f10,s10;
//decalare two nets for assign
wire candy;
wire gum;
//this is not needed as its already declared
//output reg Candy, Gum;
wire f5w,s5w,th5w,f10w,s10w;
assign gum = Gum;
assign candy = Candy;
assign s10w = f10 ;
assign f5w = s5;
assign s5w = th5;
//parameter initialization and nulling!


always @ ( posedge clk )
begin //this part is for candy
if (reset == 1)
begin
f5 <= 0; s5 <= 0; th5 <= 0; f10 <= 0; s10 <= 0;
end
if (sC == 1 )
begin
if (i10 == 1)
begin
f10 = f10 + 1;
if ( (s10 == 1) & (f5 == 1) )
Candy = f5w & s10w;
end
if ( f5 == 1 ) //this part is for 5+5+5+10
begin
f5 = f5 +1;
Candy = f5w & s5w & f10w;
end
end //end of candy probabilities

if (i5 == 1)
begin
f5 = f5 + 1;
if ( ( f5 == 1 ) & ( th5 == 1 ))
Candy = f5w & th5w;
end //end candy design for 5 5s & 2 10s +5
if ( sG ==1)
begin
if ( f5 ==1 ) //this part is for gum
begin
f5 = f5 +1;
Gum = f5w & s5w; //5+5+5
end
Gum = f5w & f10w; //5+10
end //end of Gum probabilities

end

endmodule

Regards,
Debraj
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Xilinx Employee
Xilinx Employee
10,552 Views
Registered: ‎04-16-2012

Re: Why am I getting theses ERRORS?

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Hi,

 

HDL compiler :329 error states that  you are trying to use REG data type in the Assign statements which is incorrect coding. If you want to assign any signal  using assign statements you must declare that signal as WIRE data type.

 

HDL compiler: 1660 error states that Procedural assignment to a non-register is not permitted, left-hand side should be reg/integer/time/genvar.

 

Thanks

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Highlighted
Moderator
Moderator
16,118 Views
Registered: ‎04-17-2011

Re: Why am I getting theses ERRORS?

Jump to solution

Modified non-error code:

 

module VendingMach( input clk, input sC,sG,i10, i5, reset,
//set Gum & Candy as outout reg and correct dSum declaration
output reg Gum, output reg Candy, ch, [6:0] dSum );


reg f5,s5,th5,f10,s10;
//decalare two nets for assign
wire candy;
wire gum;
//this is not needed as its already declared
//output reg Candy, Gum;
wire f5w,s5w,th5w,f10w,s10w;
assign gum = Gum;
assign candy = Candy;
assign s10w = f10 ;
assign f5w = s5;
assign s5w = th5;
//parameter initialization and nulling!


always @ ( posedge clk )
begin //this part is for candy
if (reset == 1)
begin
f5 <= 0; s5 <= 0; th5 <= 0; f10 <= 0; s10 <= 0;
end
if (sC == 1 )
begin
if (i10 == 1)
begin
f10 = f10 + 1;
if ( (s10 == 1) & (f5 == 1) )
Candy = f5w & s10w;
end
if ( f5 == 1 ) //this part is for 5+5+5+10
begin
f5 = f5 +1;
Candy = f5w & s5w & f10w;
end
end //end of candy probabilities

if (i5 == 1)
begin
f5 = f5 + 1;
if ( ( f5 == 1 ) & ( th5 == 1 ))
Candy = f5w & th5w;
end //end candy design for 5 5s & 2 10s +5
if ( sG ==1)
begin
if ( f5 ==1 ) //this part is for gum
begin
f5 = f5 +1;
Gum = f5w & s5w; //5+5+5
end
Gum = f5w & f10w; //5+10
end //end of Gum probabilities

end

endmodule

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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