I am being told that the behavioral simulation cannot find ports I instantiated from the XADC IP despite the ports clearing being declared in the module and their names matching.
This is the file I'm instantiating in the testbench:
module XADC_simulation(
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire [15 : 0] m_axis_tdata,
output wire [4 : 0] m_axis_tid,
input wire m_axis_aclk,
input wire s_axis_aclk,
input wire m_axis_resetn,
input wire dclk_in,
input wire [15 : 0] di_in,
input wire [6 : 0] daddr_in,
input wire den_in,
input wire dwe_in,
output wire drdy_out,
output wire [15 : 0] do_out,
input wire vp_in,
input wire vn_in,
input wire vauxp6,
input wire vauxn6,
output wire [4 : 0] channel_out,
output wire eoc_out,
output wire alarm_out,
output wire eos_out,
output wire busy_out
);
xadc_wiz_0 your_instance_name (
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tid(m_axis_tid),
.m_axis_aclk(m_axis_aclk), //
.s_axis_aclk(m_axis_aclk), //
.m_axis_resetn(m_axis_resetn), //
.dclk_in(dclk_in),
.di_in(16'h0),
.daddr_in({2'b00,channel_out}),
.den_in(eoc_out),
.dwe_in(1'b0),
.drdy_out(drdy_out),
.do_out(do_out),
.vp_in(1'b0),
.vn_in(1'b0),
.vauxp6(vauxp6),
.vauxn6(vauxn6),
.channel_out(channel_out),
.eoc_out(eoc_out),
.alarm_out(alarm_out),
.eos_out(eos_out),
.busy_out(busy_out)
);And this is the testbench file:
module XADC_tb(
);
wire m_axis_tvalid;
reg m_axis_tready;
wire [15 : 0] m_axis_tdata;
wire [4 : 0] m_axis_tid;
reg dclk_in;
//reg s_axis_aclk;
wire [15 : 0] di_in;
reg [6 : 0] daddr_in;
reg den_in;
reg dwe_in;
wire drdy_out;
wire [15 : 0] do_out;
reg vp_in;
reg vn_in;
reg vauxp6;
reg vauxn6;
wire [4 : 0] channel_out;
wire eoc_out;
wire alarm_out;
wire eos_out;
wire busy_out;
XADC_simulation UUT (
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tid(m_axis_tid),
.m_axis_aclk(m_axis_aclk),
//.s_axis_aclk(s_axis_aclk),
.dclk_in(dclk_in),
.di_in(16'h0),
.daddr_in({2'b00,channel_out}),
.den_in(eoc_out),
.dwe_in(1'b0),
.drdy_out(drdy_out),
.do_out(do_out),
.vp_in(vp_in),
.vn_in(vn_in),
.vauxp6(vauxp6),
.vauxn6(vauxn6),
.channel_out(channel_out),
.eoc_out(eoc_out),
.alarm_out(alarm_out),
.eos_out(eos_out),
.busy_out(busy_out)
);
initial begin
dclk_in = m_axis_aclk;
dclk_in = 1'b0;
forever #10 dclk_in = ~dclk_in;
end
endmoduleWhen I try to run a behavioral simulation (which includes a design.txt file for sample data) I am told:
- [VRFC 10-3180] cannot find port 'm_axis_resetn' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":41]
- [VRFC 10-3180] cannot find port 's_axis_aclk' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":40]
- [VRFC 10-3180] cannot find port 'm_axis_aclk' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":39]
- [VRFC 10-3180] cannot find port 'm_axis_tid' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":38]
- [VRFC 10-3180] cannot find port 'm_axis_tdata' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":37]
- [VRFC 10-3180] cannot find port 'm_axis_tready' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":36]
- [VRFC 10-3180] cannot find port 'm_axis_tvalid' on this module ["C:/Xilinx/Vivado/XADC_to_display/XADC_to_display.srcs/sources_1/new/XADC_simulation.v":35]
When I run the exact same testbench without the AXI signals (regenerate the IP without AXI4-Streaming enabled) and use only the DRP signals it has no problem finding the ports.
If I remove one of the DRP signals (such as dclk_in for example) from the port list in the XADC_simulation the errors include that as a missing port naturally but why is it including the AXI signals when they're obviously defined?
