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Adventurer
Adventurer
2,129 Views
Registered: ‎05-12-2017

Why do I need to specify a full path to xsim libraries

I'm trying to convert an existing project into batch mode. However every time I need to specify full path to libraries:

 

$ ~/.opt/Xilinx/Vivado/2017.2/bin/xvlog --sv --nolog shift_register_vip.sv -L axi4stream_vip_v1_0_1=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/axi4stream_vip_v1_0_1 -L xil_common_vip_v1_0_0=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/xil_common_vip_v1_0_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/mpiechotka/Documents/shift_register/shift_register_vip.sv" into library work
INFO: [VRFC 10-311] analyzing module master_vip
INFO: [VRFC 10-311] analyzing module shift_register_vip
$ ~/.opt/Xilinx/Vivado/2017.2/bin/xelab --nolog shift_register_vip -L axi4stream_vip_v1_0_1=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/axi4stream_vip_v1_0_1 -L xil_common_vip_v1_0_0=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/xil_common_vip_v1_0_0 -L axis_protocol_checker_v1_1_13=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/axis_protocol_checker_v1_1_13 -s shift_register_vip_sim
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /home/mpiechotka/.opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab --nolog shift_register_vip -L axi4stream_vip_v1_0_1=/home/mpiechotka/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/axi4stream_vip_v1_0_1 -L xil_common_vip_v1_0_0=/home/mpiechotka/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/xil_common_vip_v1_0_0 -L axis_protocol_checker_v1_1_13=/home/mpiechotka/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/axis_protocol_checker_v1_1_13 -s shift_register_vip_sim 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
WARNING: [VRFC 10-1770] port aclk remains unconnected for this instance [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:75]
WARNING: [VRFC 10-597] element index 8 into user_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:294]
WARNING: [VRFC 10-597] element index 8 into tuser_stage_1_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:304]
WARNING: [VRFC 10-597] element index 8 into data_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:314]
WARNING: [VRFC 10-597] element index 8 into keep_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:315]
WARNING: [VRFC 10-597] element index 8 into strb_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:316]
WARNING: [VRFC 10-597] element index 8 into tdata_stage_1_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:327]
WARNING: [VRFC 10-597] element index 8 into tkeep_stage_1_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:328]
WARNING: [VRFC 10-597] element index 8 into tstrb_stage_1_eq is out of bounds [/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axis_protocol_checker_v1_1/hdl/axis_protocol_checker_v1_1_vl_rfs.v:329]
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.axis_iface
Compiling module axi4stream_vip_v1_0_1.axi4stream_vip_v1_0_1_if(C_AXI4S...
Compiling module axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13_as...
Compiling module axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13_re...
Compiling module axis_protocol_checker_v1_1_13.axis_protocol_checker_v1_1_13_to...
Compiling module axi4stream_vip_v1_0_1.axi4stream_vip_v1_0_1_top(C_AXI4...
Compiling module work.master_vip(IN=64)
Compiling module work.shift_register_vip
Compiling package axi4stream_vip_v1_0_1.axi4stream_vip_v1_0_1_pkg
WARNING: [XSIM 43-4333] File "/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axi4stream_vip_v1_0/hdl/axi4stream_vip_v1_0_vl_rfs.sv" Line 1092 : Logical comparison involving System Verilog dynamic types not supported yet, can lead to incorrect simulation behaviour.
WARNING: [XSIM 43-4333] File "/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axi4stream_vip_v1_0/hdl/axi4stream_vip_v1_0_vl_rfs.sv" Line 1100 : Logical comparison involving System Verilog dynamic types not supported yet, can lead to incorrect simulation behaviour.
WARNING: [XSIM 43-4333] File "/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axi4stream_vip_v1_0/hdl/axi4stream_vip_v1_0_vl_rfs.sv" Line 1112 : Logical comparison involving System Verilog dynamic types not supported yet, can lead to incorrect simulation behaviour.
WARNING: [XSIM 43-4333] File "/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axi4stream_vip_v1_0/hdl/axi4stream_vip_v1_0_vl_rfs.sv" Line 1330 : Logical comparison involving System Verilog dynamic types not supported yet, can lead to incorrect simulation behaviour.
WARNING: [XSIM 43-4333] File "/wrk/2017.2/nightly/2017_06_15_1909853/packages/customer/vivado/data/ip/xilinx/axi4stream_vip_v1_0/hdl/axi4stream_vip_v1_0_vl_rfs.sv" Line 1330 : Logical comparison involving System Verilog dynamic types not supported yet, can lead to incorrect simulation behaviour.
Compiling package xil_common_vip_v1_0_0.xil_common_vip_v1_0_0_pkg
Built simulation snapshot shift_register_vip_sim

****** Webtalk v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source /home/mpiechotka/Documents/shift_register/xsim.dir/shift_register_vip_sim/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Aug 23 00:33:46 2017...

I tried to set up 'random' variables to point to directory but I cannot get it working. What am I doing wrong?

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4 Replies
Xilinx Employee
Xilinx Employee
2,112 Views
Registered: ‎07-16-2008

Re: Why do I need to specify a full path to xsim libraries

If it's pre-compiled library located in Vivado install path, I don't think you need to specify the library path. The library mapping is specified in xsim.ini. You just need to reference the logical library via -L switch.

 

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Adventurer
Adventurer
2,082 Views
Registered: ‎05-12-2017

Re: Why do I need to specify a full path to xsim libraries

I did tried it as first step:

$ cat ~/.opt/Xilinx/Vivado/2017.2/data/xsim/xsim.ini
-- Default lib mapping for Simulator
std=$RDI_DATADIR/xsim/vhdl/std
ieee=$RDI_DATADIR/xsim/vhdl/ieee
ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
vl=$RDI_DATADIR/xsim/vhdl/vl
synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
unisim=$RDI_DATADIR/xsim/vhdl/unisim
unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
unifast=$RDI_DATADIR/xsim/vhdl/unifast
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
secureip=$RDI_DATADIR/xsim/verilog/secureip
$ export RDI_DATADIR=~/.opt/Xilinx/Vivado/2017.2/data
$ ~/.opt/Xilinx/Vivado/2017.2/bin/xvlog --sv --nolog shift_register_vip.sv -L axi4stream_vip_v1_0_1 -L xil_common_vip_v1_0_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/mpiechotka/Documents/shift_register/shift_register_vip.sv" into library work
ERROR: [VRFC 10-91] axi4stream_vip_v1_0_1_pkg is not declared [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:22]
ERROR: [VRFC 10-1040] module axis_iface ignored due to previous errors [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:24]
INFO: [VRFC 10-311] analyzing module master_vip
WARNING: [VRFC 10-535] constant expression cannot contain a hierarchical identifier [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:37]
ERROR: [VRFC 10-1040] module master_vip ignored due to previous errors [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:33]
INFO: [VRFC 10-311] analyzing module shift_register_vip
ERROR: [VRFC 10-1040] module shift_register_vip ignored due to previous errors [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:68]
$ ~/.opt/Xilinx/Vivado/2017.2/bin/xvlog --sv --nolog shift_register_vip.sv -L axi4stream_vip_v1_0_1=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/axi4stream_vip_v1_0_1 -L xil_common_vip_v1_0_0=~/.opt/Xilinx/Vivado/2017.2/data/xsim/ip/xil_common_vip_v1_0_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/mpiechotka/Documents/shift_register/shift_register_vip.sv" into library work
INFO: [VRFC 10-311] analyzing module master_vip
WARNING: [VRFC 10-535] constant expression cannot contain a hierarchical identifier [/home/mpiechotka/Documents/shift_register/shift_register_vip.sv:37]
INFO: [VRFC 10-311] analyzing module shift_register_vip
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Xilinx Employee
Xilinx Employee
2,077 Views
Registered: ‎07-16-2008

Re: Why do I need to specify a full path to xsim libraries

In project mode, a new xsim.ini should be created the .sim/sim_1/behav directory, which includes IP library mapping. I'd suggest that you copy that xsim.ini to the current simulation directory.

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Adventurer
Adventurer
2,062 Views
Registered: ‎05-12-2017

Re: Why do I need to specify a full path to xsim libraries

@graces that worked though I imagine it should've work OOTB
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