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Adventurer
Adventurer
759 Views
Registered: ‎05-04-2017

Write testbench in C for rtl design

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Hi All,

I would like to no if it's possible to write a vivado testbench for a normal rtl design in C (or even python). I found that you can do it for designs created in the HLS but is it possible

also for designs that are not generated in HLS ?

Thanks in advance

--JohnXio

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1 Solution

Accepted Solutions
Moderator
Moderator
698 Views
Registered: ‎09-15-2016

Re: Write testbench in C for rtl design

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HI @johnxio ,

The Xilinx Simulator Interface (XSI) is a C/C++ application programming interface (API) to
the Xilinx Vivado Simulator (xsim) that enables a C/C++ program to serve as the test bench
for a HDL design.

For more information, please refer the below user guide Appendix-I page#249:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug900-vivado-logic-simulation.pdf 

Thanks & Regards,
Sravanthi B
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Voyager
Voyager
733 Views
Registered: ‎03-28-2016

Re: Write testbench in C for rtl design

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I am unaware of any way to simulate RTL design files with a testbench written in C or Python.

HLS is the closest thing to that in that it uses C testbenches, but HLS will not load RTL files.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Contributor
Contributor
726 Views
Registered: ‎10-25-2018

Re: Write testbench in C for rtl design

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The answer to your question is "yes", in that Vivado supports the SystemVerilog Direct Programming Interface (DPI). You would create a SV testbench and instantiate your RTL, whether it be Verilog, SystemVerilog, or VHDL, inside it. Then use the DPI to interface with your C test program.

See here for more information.

 

 

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Scholar richardhead
Scholar
719 Views
Registered: ‎08-01-2012

Re: Write testbench in C for rtl design

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While not supported at all in Vivado, if you want to use Python then there is Vunit as a python based testing framework for HDL designs.

https://vunit.github.io/

 

Then there is MyHDL where entire designs can be be written and tested in python (it generates HDL to allow synthesis, but all of the source can be written in python)

http://www.myhdl.org/

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Moderator
Moderator
699 Views
Registered: ‎09-15-2016

Re: Write testbench in C for rtl design

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HI @johnxio ,

The Xilinx Simulator Interface (XSI) is a C/C++ application programming interface (API) to
the Xilinx Vivado Simulator (xsim) that enables a C/C++ program to serve as the test bench
for a HDL design.

For more information, please refer the below user guide Appendix-I page#249:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug900-vivado-logic-simulation.pdf 

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
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Adventurer
Adventurer
676 Views
Registered: ‎05-04-2017

Re: Write testbench in C for rtl design

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Hi @richardhead
as an addition to your wonderful solutions I found also: https://cocotb.readthedocs.io/en/latest/introduction.html
Cheers
--JohnXio
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Adventurer
Adventurer
676 Views
Registered: ‎05-04-2017

Re: Write testbench in C for rtl design

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Hi Everybody,

thanks for the nice replies and suggestions, I will take a look on all those and find what is the best solution to test my HDL design. For the moment I will close the thread by accepting the official Xilinx solution.

Cheers

--Ioannis

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