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simozz
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Registered: ‎05-14-2017

Writing to AXI Slave using VIP package doesn't work

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Hello,

I am trying to simulate a design including a custom AXI4-Lite slave IP which seems to work properly in real-design, however, when I try to simulate its behavior, together with other IPs, even if I assign and send values using AXI4LITE_WRITE_BURST, values are not sent in simulation (at least I don't see any change in waveform window).

The block design is the following one:

Screenshot_2020-04-17_12-55-38.png

Screenshot_2020-04-17_13-03-19.png

System Verilog test-bench for writing to the AXI4-Lite slave is the following:

`timescale 1ns / 1ps

import axi_vip_pkg::*; import design_1_axi_vip_0_0_pkg::*; import design_1_axi_vip_1_0_pkg::*; module design_1_tb(); reg [31:0] axi_dma_base_addr, axi_dma_off_t, axi_dma_data_w, axi_dma_data_r; reg [31:0] s_axi_ctl_base_addr, s_axi_ctl_off_t, s_axi_ctl_data_w, s_axi_ctl_data_r; xil_axi_resp_t resp; reg clk_in; reg reset_in; reg pps_in; design_1_axi_vip_0_0_mst_t master_agent; // design_1_wrapper instance design_1_wrapper dut ( .clk_in(clk_in), .reset_in(reset_in), .pps_in(pps_in) ); always begin #1 clk_in <= ~clk_in; end always begin #100 pps_in <= ~pps_in; end initial begin master_agent = new("master vip agent", dut.design_1_i.axi_vip_0.inst.IF); master_agent.start_master(); #0 clk_in <= 0; reset_in <= 0; pps_in <= 0; s_axi_ctl_base_addr <= 32'h80000000; s_axi_ctl_off_t <= 32'h00000000; s_axi_ctl_data_w <= 32'h00000000; s_axi_ctl_data_r <= 32'h00000000; axi_dma_base_addr <= 32'h80010000; axi_dma_off_t <= 0; axi_dma_data_w <= 0; axi_dma_data_r <= 0; #1 reset_in <= 1; #150 s_axi_ctl_off_t <= 0; s_axi_ctl_data_w <= 1; master_agent.AXI4LITE_WRITE_BURST(s_axi_ctl_base_addr + s_axi_ctl_off_t, 0, s_axi_ctl_data_w, resp); #1000000 $finish; end endmodule

[EDIT]

I forgot to add waveform screenshot:

Screenshot_2020-04-17_13-45-04.png

[/EDIT]

Since the behavior of this AXI4-Lite slave is verified in real life through oscilloscope and register analysis from PS, what's wrong in my test-bench ?

Thanks.

s.

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dgisselq
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Registered: ‎05-21-2015

@simozz,

Tell me, in your trace, is the bus idle for the first clock period after the AXI ARESETN signal goes high (not active)?  Your trace diagram is so compressed that I can't tell, but your initial block suggests that you deactivate the reset and raise a valid signal on the same cycle--a protocol violation.

Dan

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dgisselq
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Registered: ‎05-21-2015

@simozz,

Are you sure you have those blocking (=) vs non-blocking (<=) assignments right?  In general, the clock should use a blocking assignment (=) and it should toggle.  Most of the rest of your test logic should  use non-blocking logic (<=), and it should be synchronous to the clock.

Dan

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simozz
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Registered: ‎05-14-2017

@dgisselq,

I am using just non-blocking assignments.

pps_rise signal (from this AXI4-Lite Slave IP) is toggles well in response to pps_in rising edge signal (not shown in waveform attached in 1st post).

s.

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dgisselq
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Registered: ‎05-21-2015

@simozz,

Tell me, in your trace, is the bus idle for the first clock period after the AXI ARESETN signal goes high (not active)?  Your trace diagram is so compressed that I can't tell, but your initial block suggests that you deactivate the reset and raise a valid signal on the same cycle--a protocol violation.

Dan

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simozz
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Registered: ‎05-14-2017

@dgisselq, you got it ! Nice strike .

Thank you !

s.